i82094aa.cc revision 6803:c647872c6590 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/interrupts.hh"
32#include "arch/x86/intmessage.hh"
33#include "dev/x86/i82094aa.hh"
34#include "dev/x86/i8259.hh"
35#include "mem/packet.hh"
36#include "mem/packet_access.hh"
37#include "sim/system.hh"
38
39X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
40    IntDev(this, p->int_latency),
41    latency(p->pio_latency), pioAddr(p->pio_addr),
42    extIntPic(p->external_int_pic), lowestPriorityOffset(0)
43{
44    // This assumes there's only one I/O APIC in the system
45    initialApicId = id = p->apic_id;
46    assert(id <= 0xf);
47    arbId = id;
48    regSel = 0;
49    RedirTableEntry entry = 0;
50    entry.mask = 1;
51    for (int i = 0; i < TableSize; i++) {
52        redirTable[i] = entry;
53        pinStates[i] = false;
54    }
55}
56
57Tick
58X86ISA::I82094AA::read(PacketPtr pkt)
59{
60    assert(pkt->getSize() == 4);
61    Addr offset = pkt->getAddr() - pioAddr;
62    switch(offset) {
63      case 0:
64        pkt->set<uint32_t>(regSel);
65        break;
66      case 16:
67        pkt->set<uint32_t>(readReg(regSel));
68        break;
69      default:
70        panic("Illegal read from I/O APIC.\n");
71    }
72    pkt->makeAtomicResponse();
73    return latency;
74}
75
76Tick
77X86ISA::I82094AA::write(PacketPtr pkt)
78{
79    assert(pkt->getSize() == 4);
80    Addr offset = pkt->getAddr() - pioAddr;
81    switch(offset) {
82      case 0:
83        regSel = pkt->get<uint32_t>();
84        break;
85      case 16:
86        writeReg(regSel, pkt->get<uint32_t>());
87        break;
88      default:
89        panic("Illegal write to I/O APIC.\n");
90    }
91    pkt->makeAtomicResponse();
92    return latency;
93}
94
95void
96X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
97{
98    if (offset == 0x0) {
99        id = bits(value, 27, 24);
100    } else if (offset == 0x1) {
101        // The IOAPICVER register is read only.
102    } else if (offset == 0x2) {
103        arbId = bits(value, 27, 24);
104    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
105        int index = (offset - 0x10) / 2;
106        if (offset % 2) {
107            redirTable[index].topDW = value;
108            redirTable[index].topReserved = 0;
109        } else {
110            redirTable[index].bottomDW = value;
111            redirTable[index].bottomReserved = 0;
112        }
113    } else {
114        warn("Access to undefined I/O APIC register %#x.\n", offset);
115    }
116    DPRINTF(I82094AA,
117            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
118}
119
120uint32_t
121X86ISA::I82094AA::readReg(uint8_t offset)
122{
123    uint32_t result = 0;
124    if (offset == 0x0) {
125        result = id << 24;
126    } else if (offset == 0x1) {
127        result = ((TableSize - 1) << 16) | APICVersion;
128    } else if (offset == 0x2) {
129        result = arbId << 24;
130    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
131        int index = (offset - 0x10) / 2;
132        if (offset % 2) {
133            result = redirTable[index].topDW;
134        } else {
135            result = redirTable[index].bottomDW;
136        }
137    } else {
138        warn("Access to undefined I/O APIC register %#x.\n", offset);
139    }
140    DPRINTF(I82094AA,
141            "Read %#x from I/O APIC register %#x.\n", result, offset);
142    return result;
143}
144
145void
146X86ISA::I82094AA::signalInterrupt(int line)
147{
148    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
149    assert(line < TableSize);
150    RedirTableEntry entry = redirTable[line];
151    if (entry.mask) {
152        DPRINTF(I82094AA, "Entry was masked.\n");
153        return;
154    } else {
155        TriggerIntMessage message = 0;
156        message.destination = entry.dest;
157        if (entry.deliveryMode == DeliveryMode::ExtInt) {
158            assert(extIntPic);
159            message.vector = extIntPic->getVector();
160        } else {
161            message.vector = entry.vector;
162        }
163        message.deliveryMode = entry.deliveryMode;
164        message.destMode = entry.destMode;
165        message.level = entry.polarity;
166        message.trigger = entry.trigger;
167        ApicList apics;
168        int numContexts = sys->numContexts();
169        if (message.destMode == 0) {
170            if (message.deliveryMode == DeliveryMode::LowestPriority) {
171                panic("Lowest priority delivery mode from the "
172                        "IO APIC aren't supported in physical "
173                        "destination mode.\n");
174            }
175            if (message.destination == 0xFF) {
176                for (int i = 0; i < numContexts; i++) {
177                    apics.push_back(i);
178                }
179            } else {
180                apics.push_back(message.destination);
181            }
182        } else {
183            for (int i = 0; i < numContexts; i++) {
184                std::map<int, Interrupts *>::iterator localApicIt =
185                    localApics.find(i);
186                assert(localApicIt != localApics.end());
187                Interrupts *localApic = localApicIt->second;
188                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
189                        message.destination) {
190                    apics.push_back(localApicIt->first);
191                }
192            }
193            if (message.deliveryMode == DeliveryMode::LowestPriority &&
194                    apics.size()) {
195                // The manual seems to suggest that the chipset just does
196                // something reasonable for these instead of actually using
197                // state from the local APIC. We'll just rotate an offset
198                // through the set of APICs selected above.
199                uint64_t modOffset = lowestPriorityOffset % apics.size();
200                lowestPriorityOffset++;
201                ApicList::iterator apicIt = apics.begin();
202                while (modOffset--) {
203                    apicIt++;
204                    assert(apicIt != apics.end());
205                }
206                int selected = *apicIt;
207                apics.clear();
208                apics.push_back(selected);
209            }
210        }
211        intPort->sendMessage(apics, message,
212                sys->getMemoryMode() == Enums::timing);
213    }
214}
215
216void
217X86ISA::I82094AA::raiseInterruptPin(int number)
218{
219    assert(number < TableSize);
220    if (!pinStates[number])
221        signalInterrupt(number);
222    pinStates[number] = true;
223}
224
225void
226X86ISA::I82094AA::lowerInterruptPin(int number)
227{
228    assert(number < TableSize);
229    pinStates[number] = false;
230}
231
232void
233X86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic)
234{
235    assert(localApic);
236    localApics[initialId] = localApic;
237}
238
239X86ISA::I82094AA *
240I82094AAParams::create()
241{
242    return new X86ISA::I82094AA(this);
243}
244