i82094aa.cc revision 5827:ac2c268bf4f1
1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/intmessage.hh" 32#include "dev/x86/i82094aa.hh" 33#include "dev/x86/i8259.hh" 34#include "mem/packet.hh" 35#include "mem/packet_access.hh" 36#include "sim/system.hh" 37 38X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), 39 latency(p->pio_latency), pioAddr(p->pio_addr), 40 extIntPic(p->external_int_pic) 41{ 42 // This assumes there's only one I/O APIC in the system 43 id = sys->numContexts(); 44 assert(id <= 0xf); 45 arbId = id; 46 regSel = 0; 47 RedirTableEntry entry = 0; 48 entry.mask = 1; 49 for (int i = 0; i < TableSize; i++) { 50 redirTable[i] = entry; 51 pinStates[i] = false; 52 } 53} 54 55Tick 56X86ISA::I82094AA::read(PacketPtr pkt) 57{ 58 assert(pkt->getSize() == 4); 59 Addr offset = pkt->getAddr() - pioAddr; 60 switch(offset) { 61 case 0: 62 pkt->set<uint32_t>(regSel); 63 break; 64 case 16: 65 pkt->set<uint32_t>(readReg(regSel)); 66 break; 67 default: 68 panic("Illegal read from I/O APIC.\n"); 69 } 70 return latency; 71} 72 73Tick 74X86ISA::I82094AA::write(PacketPtr pkt) 75{ 76 assert(pkt->getSize() == 4); 77 Addr offset = pkt->getAddr() - pioAddr; 78 switch(offset) { 79 case 0: 80 regSel = pkt->get<uint32_t>(); 81 break; 82 case 16: 83 writeReg(regSel, pkt->get<uint32_t>()); 84 break; 85 default: 86 panic("Illegal write to I/O APIC.\n"); 87 } 88 return latency; 89} 90 91void 92X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 93{ 94 if (offset == 0x0) { 95 id = bits(value, 27, 24); 96 } else if (offset == 0x1) { 97 // The IOAPICVER register is read only. 98 } else if (offset == 0x2) { 99 arbId = bits(value, 27, 24); 100 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 101 int index = (offset - 0x10) / 2; 102 if (offset % 2) { 103 redirTable[index].topDW = value; 104 redirTable[index].topReserved = 0; 105 } else { 106 redirTable[index].bottomDW = value; 107 redirTable[index].bottomReserved = 0; 108 } 109 } else { 110 warn("Access to undefined I/O APIC register %#x.\n", offset); 111 } 112 DPRINTF(I82094AA, 113 "Wrote %#x to I/O APIC register %#x .\n", value, offset); 114} 115 116uint32_t 117X86ISA::I82094AA::readReg(uint8_t offset) 118{ 119 uint32_t result = 0; 120 if (offset == 0x0) { 121 result = id << 24; 122 } else if (offset == 0x1) { 123 result = ((TableSize - 1) << 16) | APICVersion; 124 } else if (offset == 0x2) { 125 result = arbId << 24; 126 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 127 int index = (offset - 0x10) / 2; 128 if (offset % 2) { 129 result = redirTable[index].topDW; 130 } else { 131 result = redirTable[index].bottomDW; 132 } 133 } else { 134 warn("Access to undefined I/O APIC register %#x.\n", offset); 135 } 136 DPRINTF(I82094AA, 137 "Read %#x from I/O APIC register %#x.\n", result, offset); 138 return result; 139} 140 141void 142X86ISA::I82094AA::signalInterrupt(int line) 143{ 144 DPRINTF(I82094AA, "Received interrupt %d.\n", line); 145 assert(line < TableSize); 146 RedirTableEntry entry = redirTable[line]; 147 if (entry.mask) { 148 DPRINTF(I82094AA, "Entry was masked.\n"); 149 return; 150 } else { 151 TriggerIntMessage message; 152 message.destination = entry.dest; 153 if (entry.deliveryMode == DeliveryMode::ExtInt) { 154 assert(extIntPic); 155 message.vector = extIntPic->getVector(); 156 } else { 157 message.vector = entry.vector; 158 } 159 message.deliveryMode = entry.deliveryMode; 160 message.destMode = entry.destMode; 161 message.level = entry.polarity; 162 message.trigger = entry.trigger; 163 164 if (DeliveryMode::isReserved(entry.deliveryMode)) { 165 fatal("Tried to use reserved delivery mode " 166 "for IO APIC entry %d.\n", line); 167 } else if (DTRACE(I82094AA)) { 168 DPRINTF(I82094AA, "Delivery mode is: %s.\n", 169 DeliveryMode::names[entry.deliveryMode]); 170 DPRINTF(I82094AA, "Vector is %#x.\n", message.vector); 171 } 172 173 if (entry.destMode == 0) { 174 DPRINTF(I82094AA, 175 "Sending interrupt to APIC ID %d.\n", entry.dest); 176 PacketPtr pkt = buildIntRequest(entry.dest, message); 177 if (sys->getMemoryMode() == Enums::timing) 178 intPort->sendMessageTiming(pkt, latency); 179 else if (sys->getMemoryMode() == Enums::atomic) 180 intPort->sendMessageAtomic(pkt); 181 else 182 panic("Unrecognized memory mode.\n"); 183 } else { 184 DPRINTF(I82094AA, "Sending interrupts to APIC IDs:" 185 "%s%s%s%s%s%s%s%s\n", 186 bits((int)entry.dest, 0) ? " 0": "", 187 bits((int)entry.dest, 1) ? " 1": "", 188 bits((int)entry.dest, 2) ? " 2": "", 189 bits((int)entry.dest, 3) ? " 3": "", 190 bits((int)entry.dest, 4) ? " 4": "", 191 bits((int)entry.dest, 5) ? " 5": "", 192 bits((int)entry.dest, 6) ? " 6": "", 193 bits((int)entry.dest, 7) ? " 7": "" 194 ); 195 uint8_t dests = entry.dest; 196 uint8_t id = 0; 197 while(dests) { 198 if (dests & 0x1) { 199 PacketPtr pkt = buildIntRequest(id, message); 200 if (sys->getMemoryMode() == Enums::timing) 201 intPort->sendMessageTiming(pkt, latency); 202 else if (sys->getMemoryMode() == Enums::atomic) 203 intPort->sendMessageAtomic(pkt); 204 else 205 panic("Unrecognized memory mode.\n"); 206 } 207 dests >>= 1; 208 id++; 209 } 210 } 211 } 212} 213 214void 215X86ISA::I82094AA::raiseInterruptPin(int number) 216{ 217 assert(number < TableSize); 218 if (!pinStates[number]) 219 signalInterrupt(number); 220 pinStates[number] = true; 221} 222 223void 224X86ISA::I82094AA::lowerInterruptPin(int number) 225{ 226 assert(number < TableSize); 227 pinStates[number] = false; 228} 229 230X86ISA::I82094AA * 231I82094AAParams::create() 232{ 233 return new X86ISA::I82094AA(this); 234} 235