i82094aa.cc revision 5657:7539092b28ac 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/intmessage.hh"
32#include "dev/x86/i82094aa.hh"
33#include "dev/x86/i8259.hh"
34#include "mem/packet.hh"
35#include "mem/packet_access.hh"
36#include "sim/system.hh"
37
38X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
39   latency(p->pio_latency), pioAddr(p->pio_addr), extIntPic(NULL)
40{
41    // This assumes there's only one I/O APIC in the system
42    id = sys->getNumCPUs();
43    assert(id <= 0xf);
44    arbId = id;
45    regSel = 0;
46    RedirTableEntry entry = 0;
47    entry.mask = 1;
48    for (int i = 0; i < TableSize; i++) {
49        redirTable[i] = entry;
50    }
51}
52
53Tick
54X86ISA::I82094AA::read(PacketPtr pkt)
55{
56    assert(pkt->getSize() == 4);
57    Addr offset = pkt->getAddr() - pioAddr;
58    switch(offset) {
59      case 0:
60        pkt->set<uint32_t>(regSel);
61        break;
62      case 16:
63        pkt->set<uint32_t>(readReg(regSel));
64        break;
65      default:
66        panic("Illegal read from I/O APIC.\n");
67    }
68    return latency;
69}
70
71Tick
72X86ISA::I82094AA::write(PacketPtr pkt)
73{
74    assert(pkt->getSize() == 4);
75    Addr offset = pkt->getAddr() - pioAddr;
76    switch(offset) {
77      case 0:
78        regSel = pkt->get<uint32_t>();
79        break;
80      case 16:
81        writeReg(regSel, pkt->get<uint32_t>());
82        break;
83      default:
84        panic("Illegal write to I/O APIC.\n");
85    }
86    return latency;
87}
88
89void
90X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
91{
92    if (offset == 0x0) {
93        id = bits(value, 27, 24);
94    } else if (offset == 0x1) {
95        // The IOAPICVER register is read only.
96    } else if (offset == 0x2) {
97        arbId = bits(value, 27, 24);
98    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
99        int index = (offset - 0x10) / 2;
100        if (offset % 2) {
101            redirTable[index].topDW = value;
102            redirTable[index].topReserved = 0;
103        } else {
104            redirTable[index].bottomDW = value;
105            redirTable[index].bottomReserved = 0;
106        }
107    } else {
108        warn("Access to undefined I/O APIC register %#x.\n", offset);
109    }
110    DPRINTF(I82094AA,
111            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
112}
113
114uint32_t
115X86ISA::I82094AA::readReg(uint8_t offset)
116{
117    uint32_t result = 0;
118    if (offset == 0x0) {
119        result = id << 24;
120    } else if (offset == 0x1) {
121        result = ((TableSize - 1) << 16) | APICVersion;
122    } else if (offset == 0x2) {
123        result = arbId << 24;
124    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
125        int index = (offset - 0x10) / 2;
126        if (offset % 2) {
127            result = redirTable[index].topDW;
128        } else {
129            result = redirTable[index].bottomDW;
130        }
131    } else {
132        warn("Access to undefined I/O APIC register %#x.\n", offset);
133    }
134    DPRINTF(I82094AA,
135            "Read %#x from I/O APIC register %#x.\n", result, offset);
136    return result;
137}
138
139void
140X86ISA::I82094AA::signalInterrupt(int line)
141{
142    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
143    assert(line < TableSize);
144    RedirTableEntry entry = redirTable[line];
145    if (entry.mask) {
146        DPRINTF(I82094AA, "Entry was masked.\n");
147        return;
148    } else {
149        TriggerIntMessage message;
150        message.destination = entry.dest;
151        if (entry.deliveryMode == DeliveryMode::ExtInt) {
152            assert(extIntPic);
153            message.vector = extIntPic->getVector();
154        } else {
155            message.vector = entry.vector;
156        }
157        message.deliveryMode = entry.deliveryMode;
158        message.destMode = entry.destMode;
159        message.level = entry.polarity;
160        message.trigger = entry.trigger;
161
162        if (DeliveryMode::isReserved(entry.deliveryMode)) {
163            fatal("Tried to use reserved delivery mode "
164                    "for IO APIC entry %d.\n", line);
165        } else if (DTRACE(I82094AA)) {
166            DPRINTF(I82094AA, "Delivery mode is: %s.\n",
167                    DeliveryMode::names[entry.deliveryMode]);
168            DPRINTF(I82094AA, "Vector is %#x.\n", message.vector);
169        }
170
171        if (entry.destMode == 0) {
172            DPRINTF(I82094AA,
173                    "Sending interrupt to APIC ID %d.\n", entry.dest);
174            PacketPtr pkt = buildIntRequest(entry.dest, message);
175            if (sys->getMemoryMode() == Enums::timing)
176                intPort->sendMessageTiming(pkt, latency);
177            else if (sys->getMemoryMode() == Enums::atomic)
178                intPort->sendMessageAtomic(pkt);
179            else
180                panic("Unrecognized memory mode.\n");
181        } else {
182            DPRINTF(I82094AA, "Sending interrupts to APIC IDs:"
183                    "%s%s%s%s%s%s%s%s\n",
184                    bits((int)entry.dest, 0) ? " 0": "",
185                    bits((int)entry.dest, 1) ? " 1": "",
186                    bits((int)entry.dest, 2) ? " 2": "",
187                    bits((int)entry.dest, 3) ? " 3": "",
188                    bits((int)entry.dest, 4) ? " 4": "",
189                    bits((int)entry.dest, 5) ? " 5": "",
190                    bits((int)entry.dest, 6) ? " 6": "",
191                    bits((int)entry.dest, 7) ? " 7": ""
192                    );
193            uint8_t dests = entry.dest;
194            uint8_t id = 0;
195            while(dests) {
196                if (dests & 0x1) {
197                    PacketPtr pkt = buildIntRequest(id, message);
198                    if (sys->getMemoryMode() == Enums::timing)
199                        intPort->sendMessageTiming(pkt, latency);
200                    else if (sys->getMemoryMode() == Enums::atomic)
201                        intPort->sendMessageAtomic(pkt);
202                    else
203                        panic("Unrecognized memory mode.\n");
204                }
205                dests >>= 1;
206                id++;
207            }
208        }
209    }
210}
211
212X86ISA::I82094AA *
213I82094AAParams::create()
214{
215    return new X86ISA::I82094AA(this);
216}
217