i82094aa.cc revision 5643:2b1611137af4
1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "dev/x86/i82094aa.hh" 32#include "mem/packet.hh" 33#include "mem/packet_access.hh" 34#include "sim/system.hh" 35 36X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), 37 latency(p->pio_latency), pioAddr(p->pio_addr) 38{ 39 // This assumes there's only one I/O APIC in the system 40 id = sys->getNumCPUs(); 41 assert(id <= 0xf); 42 arbId = id; 43 regSel = 0; 44 memset(redirTable, 0, sizeof(RedirTableEntry) * TableSize); 45} 46 47Tick 48X86ISA::I82094AA::read(PacketPtr pkt) 49{ 50 assert(pkt->getSize() == 4); 51 Addr offset = pkt->getAddr() - pioAddr; 52 switch(offset) { 53 case 0: 54 pkt->set<uint32_t>(regSel); 55 break; 56 case 16: 57 pkt->set<uint32_t>(readReg(regSel)); 58 break; 59 default: 60 panic("Illegal read from I/O APIC.\n"); 61 } 62 return latency; 63} 64 65Tick 66X86ISA::I82094AA::write(PacketPtr pkt) 67{ 68 assert(pkt->getSize() == 4); 69 Addr offset = pkt->getAddr() - pioAddr; 70 switch(offset) { 71 case 0: 72 regSel = pkt->get<uint32_t>(); 73 break; 74 case 16: 75 writeReg(regSel, pkt->get<uint32_t>()); 76 break; 77 default: 78 panic("Illegal write to I/O APIC.\n"); 79 } 80 return latency; 81} 82 83void 84X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 85{ 86 if (offset == 0x0) { 87 id = bits(value, 27, 24); 88 } else if (offset == 0x1) { 89 // The IOAPICVER register is read only. 90 } else if (offset == 0x2) { 91 arbId = bits(value, 27, 24); 92 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 93 int index = (offset - 0x10) / 2; 94 if (offset % 2) { 95 redirTable[index].topDW = value; 96 redirTable[index].topReserved = 0; 97 } else { 98 redirTable[index].bottomDW = value; 99 redirTable[index].bottomReserved = 0; 100 } 101 } else { 102 warn("Access to undefined I/O APIC register %#x.\n", offset); 103 } 104 DPRINTF(I82094AA, 105 "Wrote %#x to I/O APIC register %#x .\n", value, offset); 106} 107 108uint32_t 109X86ISA::I82094AA::readReg(uint8_t offset) 110{ 111 uint32_t result = 0; 112 if (offset == 0x0) { 113 result = id << 24; 114 } else if (offset == 0x1) { 115 result = ((TableSize - 1) << 16) | APICVersion; 116 } else if (offset == 0x2) { 117 result = arbId << 24; 118 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 119 int index = (offset - 0x10) / 2; 120 if (offset % 2) { 121 result = redirTable[index].topDW; 122 } else { 123 result = redirTable[index].bottomDW; 124 } 125 } else { 126 warn("Access to undefined I/O APIC register %#x.\n", offset); 127 } 128 DPRINTF(I82094AA, 129 "Read %#x from I/O APIC register %#x.\n", result, offset); 130 return result; 131} 132 133void 134X86ISA::I82094AA::signalInterrupt(int line) 135{ 136 DPRINTF(I82094AA, "Received interrupt %d.\n", line); 137 assert(line < TableSize); 138 RedirTableEntry entry = redirTable[line]; 139 if (entry.mask) { 140 DPRINTF(I82094AA, "Entry was masked.\n"); 141 return; 142 } else { 143 if (entry.destMode == 0) { 144 DPRINTF(I82094AA, 145 "Would send interrupt to APIC ID %d.\n", entry.dest); 146 } else { 147 DPRINTF(I82094AA, "Would send interrupts to APIC IDs:" 148 "%s%s%s%s%s%s%s%s\n", 149 bits((int)entry.dest, 0) ? " 0": "", 150 bits((int)entry.dest, 1) ? " 1": "", 151 bits((int)entry.dest, 2) ? " 2": "", 152 bits((int)entry.dest, 3) ? " 3": "", 153 bits((int)entry.dest, 4) ? " 4": "", 154 bits((int)entry.dest, 5) ? " 5": "", 155 bits((int)entry.dest, 6) ? " 6": "", 156 bits((int)entry.dest, 7) ? " 7": "" 157 ); 158 } 159 switch(entry.deliveryMode) { 160 case 0: 161 DPRINTF(I82094AA, "Delivery mode is: Fixed.\n"); 162 break; 163 case 1: 164 DPRINTF(I82094AA, "Delivery mode is: Lowest Priority.\n"); 165 break; 166 case 2: 167 DPRINTF(I82094AA, "Delivery mode is: SMI.\n"); 168 break; 169 case 3: 170 fatal("Tried to use reserved delivery mode " 171 "for IO APIC entry %d.\n", line); 172 break; 173 case 4: 174 DPRINTF(I82094AA, "Delivery mode is: NMI.\n"); 175 break; 176 case 5: 177 DPRINTF(I82094AA, "Delivery mode is: INIT.\n"); 178 break; 179 case 6: 180 fatal("Tried to use reserved delivery mode " 181 "for IO APIC entry %d.\n", line); 182 break; 183 case 7: 184 DPRINTF(I82094AA, "Delivery mode is: ExtINT.\n"); 185 break; 186 } 187 DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector); 188 } 189} 190 191X86ISA::I82094AA * 192I82094AAParams::create() 193{ 194 return new X86ISA::I82094AA(this); 195} 196