i82094aa.cc revision 14291:722551795497 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "dev/x86/i82094aa.hh"
32
33#include "arch/x86/interrupts.hh"
34#include "arch/x86/intmessage.hh"
35#include "cpu/base.hh"
36#include "debug/I82094AA.hh"
37#include "dev/x86/i8259.hh"
38#include "mem/packet.hh"
39#include "mem/packet_access.hh"
40#include "sim/system.hh"
41
42X86ISA::I82094AA::I82094AA(Params *p)
43    : BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
44      extIntPic(p->external_int_pic), lowestPriorityOffset(0)
45{
46    // This assumes there's only one I/O APIC in the system and since the apic
47    // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
48    // be less than 0xff
49
50    assert(p->apic_id < 0xff);
51    initialApicId = id = p->apic_id;
52    arbId = id;
53    regSel = 0;
54    RedirTableEntry entry = 0;
55    entry.mask = 1;
56    for (int i = 0; i < TableSize; i++) {
57        redirTable[i] = entry;
58        pinStates[i] = false;
59    }
60
61    for (int i = 0; i < p->port_inputs_connection_count; i++)
62        inputs.push_back(new IntSinkPin<I82094AA>(
63                    csprintf("%s.inputs[%d]", name(), i), i, this));
64}
65
66void
67X86ISA::I82094AA::init()
68{
69    // The io apic must register its address ranges on both its pio port
70    // via the piodevice init() function and its int port that it inherited
71    // from IntDevice.  Note IntDevice is not a SimObject itself.
72
73    BasicPioDevice::init();
74    IntDevice::init();
75}
76
77Port &
78X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
79{
80    if (if_name == "int_master")
81        return intMasterPort;
82    if (if_name == "inputs")
83        return *inputs.at(idx);
84    else
85        return BasicPioDevice::getPort(if_name, idx);
86}
87
88AddrRangeList
89X86ISA::I82094AA::getIntAddrRange() const
90{
91    AddrRangeList ranges;
92    ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
93                             x86InterruptAddress(initialApicId, 0) +
94                             PhysAddrAPICRangeSize));
95    return ranges;
96}
97
98Tick
99X86ISA::I82094AA::recvResponse(PacketPtr pkt)
100{
101    // Packet instantiated calling sendMessage() in signalInterrupt()
102    delete pkt;
103    return 0;
104}
105
106Tick
107X86ISA::I82094AA::read(PacketPtr pkt)
108{
109    assert(pkt->getSize() == 4);
110    Addr offset = pkt->getAddr() - pioAddr;
111    switch(offset) {
112      case 0:
113        pkt->setLE<uint32_t>(regSel);
114        break;
115      case 16:
116        pkt->setLE<uint32_t>(readReg(regSel));
117        break;
118      default:
119        panic("Illegal read from I/O APIC.\n");
120    }
121    pkt->makeAtomicResponse();
122    return pioDelay;
123}
124
125Tick
126X86ISA::I82094AA::write(PacketPtr pkt)
127{
128    assert(pkt->getSize() == 4);
129    Addr offset = pkt->getAddr() - pioAddr;
130    switch(offset) {
131      case 0:
132        regSel = pkt->getLE<uint32_t>();
133        break;
134      case 16:
135        writeReg(regSel, pkt->getLE<uint32_t>());
136        break;
137      default:
138        panic("Illegal write to I/O APIC.\n");
139    }
140    pkt->makeAtomicResponse();
141    return pioDelay;
142}
143
144void
145X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
146{
147    if (offset == 0x0) {
148        id = bits(value, 31, 24);
149    } else if (offset == 0x1) {
150        // The IOAPICVER register is read only.
151    } else if (offset == 0x2) {
152        arbId = bits(value, 31, 24);
153    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
154        int index = (offset - 0x10) / 2;
155        if (offset % 2) {
156            redirTable[index].topDW = value;
157            redirTable[index].topReserved = 0;
158        } else {
159            redirTable[index].bottomDW = value;
160            redirTable[index].bottomReserved = 0;
161        }
162    } else {
163        warn("Access to undefined I/O APIC register %#x.\n", offset);
164    }
165    DPRINTF(I82094AA,
166            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
167}
168
169uint32_t
170X86ISA::I82094AA::readReg(uint8_t offset)
171{
172    uint32_t result = 0;
173    if (offset == 0x0) {
174        result = id << 24;
175    } else if (offset == 0x1) {
176        result = ((TableSize - 1) << 16) | APICVersion;
177    } else if (offset == 0x2) {
178        result = arbId << 24;
179    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
180        int index = (offset - 0x10) / 2;
181        if (offset % 2) {
182            result = redirTable[index].topDW;
183        } else {
184            result = redirTable[index].bottomDW;
185        }
186    } else {
187        warn("Access to undefined I/O APIC register %#x.\n", offset);
188    }
189    DPRINTF(I82094AA,
190            "Read %#x from I/O APIC register %#x.\n", result, offset);
191    return result;
192}
193
194void
195X86ISA::I82094AA::signalInterrupt(int line)
196{
197    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
198    assert(line < TableSize);
199    RedirTableEntry entry = redirTable[line];
200    if (entry.mask) {
201        DPRINTF(I82094AA, "Entry was masked.\n");
202        return;
203    } else {
204        TriggerIntMessage message = 0;
205        message.destination = entry.dest;
206        if (entry.deliveryMode == DeliveryMode::ExtInt) {
207            assert(extIntPic);
208            message.vector = extIntPic->getVector();
209        } else {
210            message.vector = entry.vector;
211        }
212        message.deliveryMode = entry.deliveryMode;
213        message.destMode = entry.destMode;
214        message.level = entry.polarity;
215        message.trigger = entry.trigger;
216        ApicList apics;
217        int numContexts = sys->numContexts();
218        if (message.destMode == 0) {
219            if (message.deliveryMode == DeliveryMode::LowestPriority) {
220                panic("Lowest priority delivery mode from the "
221                        "IO APIC aren't supported in physical "
222                        "destination mode.\n");
223            }
224            if (message.destination == 0xFF) {
225                for (int i = 0; i < numContexts; i++) {
226                    apics.push_back(i);
227                }
228            } else {
229                apics.push_back(message.destination);
230            }
231        } else {
232            for (int i = 0; i < numContexts; i++) {
233                Interrupts *localApic = sys->getThreadContext(i)->
234                    getCpuPtr()->getInterruptController(0);
235                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
236                        message.destination) {
237                    apics.push_back(localApic->getInitialApicId());
238                }
239            }
240            if (message.deliveryMode == DeliveryMode::LowestPriority &&
241                    apics.size()) {
242                // The manual seems to suggest that the chipset just does
243                // something reasonable for these instead of actually using
244                // state from the local APIC. We'll just rotate an offset
245                // through the set of APICs selected above.
246                uint64_t modOffset = lowestPriorityOffset % apics.size();
247                lowestPriorityOffset++;
248                ApicList::iterator apicIt = apics.begin();
249                while (modOffset--) {
250                    apicIt++;
251                    assert(apicIt != apics.end());
252                }
253                int selected = *apicIt;
254                apics.clear();
255                apics.push_back(selected);
256            }
257        }
258        intMasterPort.sendMessage(apics, message, sys->isTimingMode());
259    }
260}
261
262void
263X86ISA::I82094AA::raiseInterruptPin(int number)
264{
265    assert(number < TableSize);
266    if (!pinStates[number])
267        signalInterrupt(number);
268    pinStates[number] = true;
269}
270
271void
272X86ISA::I82094AA::lowerInterruptPin(int number)
273{
274    assert(number < TableSize);
275    pinStates[number] = false;
276}
277
278void
279X86ISA::I82094AA::serialize(CheckpointOut &cp) const
280{
281    uint64_t* redirTableArray = (uint64_t*)redirTable;
282    SERIALIZE_SCALAR(regSel);
283    SERIALIZE_SCALAR(initialApicId);
284    SERIALIZE_SCALAR(id);
285    SERIALIZE_SCALAR(arbId);
286    SERIALIZE_SCALAR(lowestPriorityOffset);
287    SERIALIZE_ARRAY(redirTableArray, TableSize);
288    SERIALIZE_ARRAY(pinStates, TableSize);
289}
290
291void
292X86ISA::I82094AA::unserialize(CheckpointIn &cp)
293{
294    uint64_t redirTableArray[TableSize];
295    UNSERIALIZE_SCALAR(regSel);
296    UNSERIALIZE_SCALAR(initialApicId);
297    UNSERIALIZE_SCALAR(id);
298    UNSERIALIZE_SCALAR(arbId);
299    UNSERIALIZE_SCALAR(lowestPriorityOffset);
300    UNSERIALIZE_ARRAY(redirTableArray, TableSize);
301    UNSERIALIZE_ARRAY(pinStates, TableSize);
302    for (int i = 0; i < TableSize; i++) {
303        redirTable[i] = (RedirTableEntry)redirTableArray[i];
304    }
305}
306
307X86ISA::I82094AA *
308I82094AAParams::create()
309{
310    return new X86ISA::I82094AA(this);
311}
312