i82094aa.cc revision 6803
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 316138Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 325651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 335643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 345657Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 355643Sgblack@eecs.umich.edu#include "mem/packet.hh" 365643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 375643Sgblack@eecs.umich.edu#include "sim/system.hh" 385643Sgblack@eecs.umich.edu 396803Sgblack@eecs.umich.eduX86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), 406803Sgblack@eecs.umich.edu IntDev(this, p->int_latency), 415827Sgblack@eecs.umich.edu latency(p->pio_latency), pioAddr(p->pio_addr), 426139Sgblack@eecs.umich.edu extIntPic(p->external_int_pic), lowestPriorityOffset(0) 435643Sgblack@eecs.umich.edu{ 445643Sgblack@eecs.umich.edu // This assumes there's only one I/O APIC in the system 456136Sgblack@eecs.umich.edu initialApicId = id = p->apic_id; 465643Sgblack@eecs.umich.edu assert(id <= 0xf); 475643Sgblack@eecs.umich.edu arbId = id; 485643Sgblack@eecs.umich.edu regSel = 0; 495653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 505653Sgblack@eecs.umich.edu entry.mask = 1; 515653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 525653Sgblack@eecs.umich.edu redirTable[i] = entry; 535827Sgblack@eecs.umich.edu pinStates[i] = false; 545653Sgblack@eecs.umich.edu } 555643Sgblack@eecs.umich.edu} 565643Sgblack@eecs.umich.edu 575643Sgblack@eecs.umich.eduTick 585643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 595643Sgblack@eecs.umich.edu{ 605643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 615643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 625643Sgblack@eecs.umich.edu switch(offset) { 635643Sgblack@eecs.umich.edu case 0: 645643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 655643Sgblack@eecs.umich.edu break; 665643Sgblack@eecs.umich.edu case 16: 675643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 685643Sgblack@eecs.umich.edu break; 695643Sgblack@eecs.umich.edu default: 705643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 715643Sgblack@eecs.umich.edu } 725898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 735643Sgblack@eecs.umich.edu return latency; 745643Sgblack@eecs.umich.edu} 755643Sgblack@eecs.umich.edu 765643Sgblack@eecs.umich.eduTick 775643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 785643Sgblack@eecs.umich.edu{ 795643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 805643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 815643Sgblack@eecs.umich.edu switch(offset) { 825643Sgblack@eecs.umich.edu case 0: 835643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 845643Sgblack@eecs.umich.edu break; 855643Sgblack@eecs.umich.edu case 16: 865643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 875643Sgblack@eecs.umich.edu break; 885643Sgblack@eecs.umich.edu default: 895643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 905643Sgblack@eecs.umich.edu } 915898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 925643Sgblack@eecs.umich.edu return latency; 935643Sgblack@eecs.umich.edu} 945643Sgblack@eecs.umich.edu 955643Sgblack@eecs.umich.eduvoid 965643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 975643Sgblack@eecs.umich.edu{ 985643Sgblack@eecs.umich.edu if (offset == 0x0) { 995643Sgblack@eecs.umich.edu id = bits(value, 27, 24); 1005643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1015643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 1025643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1035643Sgblack@eecs.umich.edu arbId = bits(value, 27, 24); 1045643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1055643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1065643Sgblack@eecs.umich.edu if (offset % 2) { 1075643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1085643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1095643Sgblack@eecs.umich.edu } else { 1105643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1115643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1125643Sgblack@eecs.umich.edu } 1135643Sgblack@eecs.umich.edu } else { 1145643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1155643Sgblack@eecs.umich.edu } 1165643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1175643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1185643Sgblack@eecs.umich.edu} 1195643Sgblack@eecs.umich.edu 1205643Sgblack@eecs.umich.eduuint32_t 1215643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1225643Sgblack@eecs.umich.edu{ 1235643Sgblack@eecs.umich.edu uint32_t result = 0; 1245643Sgblack@eecs.umich.edu if (offset == 0x0) { 1255643Sgblack@eecs.umich.edu result = id << 24; 1265643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1275643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1285643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1295643Sgblack@eecs.umich.edu result = arbId << 24; 1305643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1315643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1325643Sgblack@eecs.umich.edu if (offset % 2) { 1335643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1345643Sgblack@eecs.umich.edu } else { 1355643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1365643Sgblack@eecs.umich.edu } 1375643Sgblack@eecs.umich.edu } else { 1385643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1395643Sgblack@eecs.umich.edu } 1405643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1415643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1425643Sgblack@eecs.umich.edu return result; 1435643Sgblack@eecs.umich.edu} 1445643Sgblack@eecs.umich.edu 1455643Sgblack@eecs.umich.eduvoid 1465643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1475643Sgblack@eecs.umich.edu{ 1485643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1495643Sgblack@eecs.umich.edu assert(line < TableSize); 1505643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1515643Sgblack@eecs.umich.edu if (entry.mask) { 1525643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1535643Sgblack@eecs.umich.edu return; 1545643Sgblack@eecs.umich.edu } else { 1556712Snate@binkert.org TriggerIntMessage message = 0; 1565651Sgblack@eecs.umich.edu message.destination = entry.dest; 1575657Sgblack@eecs.umich.edu if (entry.deliveryMode == DeliveryMode::ExtInt) { 1585657Sgblack@eecs.umich.edu assert(extIntPic); 1595657Sgblack@eecs.umich.edu message.vector = extIntPic->getVector(); 1605657Sgblack@eecs.umich.edu } else { 1615657Sgblack@eecs.umich.edu message.vector = entry.vector; 1625657Sgblack@eecs.umich.edu } 1635651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 1645651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 1655654Sgblack@eecs.umich.edu message.level = entry.polarity; 1665654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 1676138Sgblack@eecs.umich.edu ApicList apics; 1686138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 1696138Sgblack@eecs.umich.edu if (message.destMode == 0) { 1706138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 1716138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode from the " 1726138Sgblack@eecs.umich.edu "IO APIC aren't supported in physical " 1736138Sgblack@eecs.umich.edu "destination mode.\n"); 1746138Sgblack@eecs.umich.edu } 1756138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 1766138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 1776138Sgblack@eecs.umich.edu apics.push_back(i); 1786138Sgblack@eecs.umich.edu } 1796138Sgblack@eecs.umich.edu } else { 1806138Sgblack@eecs.umich.edu apics.push_back(message.destination); 1816138Sgblack@eecs.umich.edu } 1826138Sgblack@eecs.umich.edu } else { 1836138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 1846138Sgblack@eecs.umich.edu std::map<int, Interrupts *>::iterator localApicIt = 1856138Sgblack@eecs.umich.edu localApics.find(i); 1866138Sgblack@eecs.umich.edu assert(localApicIt != localApics.end()); 1876138Sgblack@eecs.umich.edu Interrupts *localApic = localApicIt->second; 1886138Sgblack@eecs.umich.edu if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 1896138Sgblack@eecs.umich.edu message.destination) { 1906138Sgblack@eecs.umich.edu apics.push_back(localApicIt->first); 1916138Sgblack@eecs.umich.edu } 1926138Sgblack@eecs.umich.edu } 1936139Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority && 1946139Sgblack@eecs.umich.edu apics.size()) { 1956139Sgblack@eecs.umich.edu // The manual seems to suggest that the chipset just does 1966139Sgblack@eecs.umich.edu // something reasonable for these instead of actually using 1976139Sgblack@eecs.umich.edu // state from the local APIC. We'll just rotate an offset 1986139Sgblack@eecs.umich.edu // through the set of APICs selected above. 1996139Sgblack@eecs.umich.edu uint64_t modOffset = lowestPriorityOffset % apics.size(); 2006139Sgblack@eecs.umich.edu lowestPriorityOffset++; 2016139Sgblack@eecs.umich.edu ApicList::iterator apicIt = apics.begin(); 2026139Sgblack@eecs.umich.edu while (modOffset--) { 2036139Sgblack@eecs.umich.edu apicIt++; 2046139Sgblack@eecs.umich.edu assert(apicIt != apics.end()); 2056139Sgblack@eecs.umich.edu } 2066139Sgblack@eecs.umich.edu int selected = *apicIt; 2076139Sgblack@eecs.umich.edu apics.clear(); 2086139Sgblack@eecs.umich.edu apics.push_back(selected); 2096138Sgblack@eecs.umich.edu } 2106138Sgblack@eecs.umich.edu } 2116138Sgblack@eecs.umich.edu intPort->sendMessage(apics, message, 2126138Sgblack@eecs.umich.edu sys->getMemoryMode() == Enums::timing); 2135643Sgblack@eecs.umich.edu } 2145643Sgblack@eecs.umich.edu} 2155643Sgblack@eecs.umich.edu 2165827Sgblack@eecs.umich.eduvoid 2175827Sgblack@eecs.umich.eduX86ISA::I82094AA::raiseInterruptPin(int number) 2185827Sgblack@eecs.umich.edu{ 2195827Sgblack@eecs.umich.edu assert(number < TableSize); 2205827Sgblack@eecs.umich.edu if (!pinStates[number]) 2215827Sgblack@eecs.umich.edu signalInterrupt(number); 2225827Sgblack@eecs.umich.edu pinStates[number] = true; 2235827Sgblack@eecs.umich.edu} 2245827Sgblack@eecs.umich.edu 2255827Sgblack@eecs.umich.eduvoid 2265827Sgblack@eecs.umich.eduX86ISA::I82094AA::lowerInterruptPin(int number) 2275827Sgblack@eecs.umich.edu{ 2285827Sgblack@eecs.umich.edu assert(number < TableSize); 2295827Sgblack@eecs.umich.edu pinStates[number] = false; 2305827Sgblack@eecs.umich.edu} 2315827Sgblack@eecs.umich.edu 2326137Sgblack@eecs.umich.eduvoid 2336137Sgblack@eecs.umich.eduX86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic) 2346137Sgblack@eecs.umich.edu{ 2356137Sgblack@eecs.umich.edu assert(localApic); 2366137Sgblack@eecs.umich.edu localApics[initialId] = localApic; 2376137Sgblack@eecs.umich.edu} 2386137Sgblack@eecs.umich.edu 2395643Sgblack@eecs.umich.eduX86ISA::I82094AA * 2405643Sgblack@eecs.umich.eduI82094AAParams::create() 2415643Sgblack@eecs.umich.edu{ 2425643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 2435643Sgblack@eecs.umich.edu} 244