i82094aa.cc revision 6712
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 316138Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 325651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 335643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 345657Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 355643Sgblack@eecs.umich.edu#include "mem/packet.hh" 365643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 375643Sgblack@eecs.umich.edu#include "sim/system.hh" 385643Sgblack@eecs.umich.edu 395651Sgblack@eecs.umich.eduX86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), 405827Sgblack@eecs.umich.edu latency(p->pio_latency), pioAddr(p->pio_addr), 416139Sgblack@eecs.umich.edu extIntPic(p->external_int_pic), lowestPriorityOffset(0) 425643Sgblack@eecs.umich.edu{ 435643Sgblack@eecs.umich.edu // This assumes there's only one I/O APIC in the system 446136Sgblack@eecs.umich.edu initialApicId = id = p->apic_id; 455643Sgblack@eecs.umich.edu assert(id <= 0xf); 465643Sgblack@eecs.umich.edu arbId = id; 475643Sgblack@eecs.umich.edu regSel = 0; 485653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 495653Sgblack@eecs.umich.edu entry.mask = 1; 505653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 515653Sgblack@eecs.umich.edu redirTable[i] = entry; 525827Sgblack@eecs.umich.edu pinStates[i] = false; 535653Sgblack@eecs.umich.edu } 545643Sgblack@eecs.umich.edu} 555643Sgblack@eecs.umich.edu 565643Sgblack@eecs.umich.eduTick 575643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 585643Sgblack@eecs.umich.edu{ 595643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 605643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 615643Sgblack@eecs.umich.edu switch(offset) { 625643Sgblack@eecs.umich.edu case 0: 635643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 645643Sgblack@eecs.umich.edu break; 655643Sgblack@eecs.umich.edu case 16: 665643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 675643Sgblack@eecs.umich.edu break; 685643Sgblack@eecs.umich.edu default: 695643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 705643Sgblack@eecs.umich.edu } 715898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 725643Sgblack@eecs.umich.edu return latency; 735643Sgblack@eecs.umich.edu} 745643Sgblack@eecs.umich.edu 755643Sgblack@eecs.umich.eduTick 765643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 775643Sgblack@eecs.umich.edu{ 785643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 795643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 805643Sgblack@eecs.umich.edu switch(offset) { 815643Sgblack@eecs.umich.edu case 0: 825643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 835643Sgblack@eecs.umich.edu break; 845643Sgblack@eecs.umich.edu case 16: 855643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 865643Sgblack@eecs.umich.edu break; 875643Sgblack@eecs.umich.edu default: 885643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 895643Sgblack@eecs.umich.edu } 905898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 915643Sgblack@eecs.umich.edu return latency; 925643Sgblack@eecs.umich.edu} 935643Sgblack@eecs.umich.edu 945643Sgblack@eecs.umich.eduvoid 955643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 965643Sgblack@eecs.umich.edu{ 975643Sgblack@eecs.umich.edu if (offset == 0x0) { 985643Sgblack@eecs.umich.edu id = bits(value, 27, 24); 995643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1005643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 1015643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1025643Sgblack@eecs.umich.edu arbId = bits(value, 27, 24); 1035643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1045643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1055643Sgblack@eecs.umich.edu if (offset % 2) { 1065643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1075643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1085643Sgblack@eecs.umich.edu } else { 1095643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1105643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1115643Sgblack@eecs.umich.edu } 1125643Sgblack@eecs.umich.edu } else { 1135643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1145643Sgblack@eecs.umich.edu } 1155643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1165643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1175643Sgblack@eecs.umich.edu} 1185643Sgblack@eecs.umich.edu 1195643Sgblack@eecs.umich.eduuint32_t 1205643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1215643Sgblack@eecs.umich.edu{ 1225643Sgblack@eecs.umich.edu uint32_t result = 0; 1235643Sgblack@eecs.umich.edu if (offset == 0x0) { 1245643Sgblack@eecs.umich.edu result = id << 24; 1255643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1265643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1275643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1285643Sgblack@eecs.umich.edu result = arbId << 24; 1295643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1305643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1315643Sgblack@eecs.umich.edu if (offset % 2) { 1325643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1335643Sgblack@eecs.umich.edu } else { 1345643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1355643Sgblack@eecs.umich.edu } 1365643Sgblack@eecs.umich.edu } else { 1375643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1385643Sgblack@eecs.umich.edu } 1395643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1405643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1415643Sgblack@eecs.umich.edu return result; 1425643Sgblack@eecs.umich.edu} 1435643Sgblack@eecs.umich.edu 1445643Sgblack@eecs.umich.eduvoid 1455643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1465643Sgblack@eecs.umich.edu{ 1475643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1485643Sgblack@eecs.umich.edu assert(line < TableSize); 1495643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1505643Sgblack@eecs.umich.edu if (entry.mask) { 1515643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1525643Sgblack@eecs.umich.edu return; 1535643Sgblack@eecs.umich.edu } else { 1546712Snate@binkert.org TriggerIntMessage message = 0; 1555651Sgblack@eecs.umich.edu message.destination = entry.dest; 1565657Sgblack@eecs.umich.edu if (entry.deliveryMode == DeliveryMode::ExtInt) { 1575657Sgblack@eecs.umich.edu assert(extIntPic); 1585657Sgblack@eecs.umich.edu message.vector = extIntPic->getVector(); 1595657Sgblack@eecs.umich.edu } else { 1605657Sgblack@eecs.umich.edu message.vector = entry.vector; 1615657Sgblack@eecs.umich.edu } 1625651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 1635651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 1645654Sgblack@eecs.umich.edu message.level = entry.polarity; 1655654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 1666138Sgblack@eecs.umich.edu ApicList apics; 1676138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 1686138Sgblack@eecs.umich.edu if (message.destMode == 0) { 1696138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 1706138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode from the " 1716138Sgblack@eecs.umich.edu "IO APIC aren't supported in physical " 1726138Sgblack@eecs.umich.edu "destination mode.\n"); 1736138Sgblack@eecs.umich.edu } 1746138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 1756138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 1766138Sgblack@eecs.umich.edu apics.push_back(i); 1776138Sgblack@eecs.umich.edu } 1786138Sgblack@eecs.umich.edu } else { 1796138Sgblack@eecs.umich.edu apics.push_back(message.destination); 1806138Sgblack@eecs.umich.edu } 1816138Sgblack@eecs.umich.edu } else { 1826138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 1836138Sgblack@eecs.umich.edu std::map<int, Interrupts *>::iterator localApicIt = 1846138Sgblack@eecs.umich.edu localApics.find(i); 1856138Sgblack@eecs.umich.edu assert(localApicIt != localApics.end()); 1866138Sgblack@eecs.umich.edu Interrupts *localApic = localApicIt->second; 1876138Sgblack@eecs.umich.edu if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 1886138Sgblack@eecs.umich.edu message.destination) { 1896138Sgblack@eecs.umich.edu apics.push_back(localApicIt->first); 1906138Sgblack@eecs.umich.edu } 1916138Sgblack@eecs.umich.edu } 1926139Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority && 1936139Sgblack@eecs.umich.edu apics.size()) { 1946139Sgblack@eecs.umich.edu // The manual seems to suggest that the chipset just does 1956139Sgblack@eecs.umich.edu // something reasonable for these instead of actually using 1966139Sgblack@eecs.umich.edu // state from the local APIC. We'll just rotate an offset 1976139Sgblack@eecs.umich.edu // through the set of APICs selected above. 1986139Sgblack@eecs.umich.edu uint64_t modOffset = lowestPriorityOffset % apics.size(); 1996139Sgblack@eecs.umich.edu lowestPriorityOffset++; 2006139Sgblack@eecs.umich.edu ApicList::iterator apicIt = apics.begin(); 2016139Sgblack@eecs.umich.edu while (modOffset--) { 2026139Sgblack@eecs.umich.edu apicIt++; 2036139Sgblack@eecs.umich.edu assert(apicIt != apics.end()); 2046139Sgblack@eecs.umich.edu } 2056139Sgblack@eecs.umich.edu int selected = *apicIt; 2066139Sgblack@eecs.umich.edu apics.clear(); 2076139Sgblack@eecs.umich.edu apics.push_back(selected); 2086138Sgblack@eecs.umich.edu } 2096138Sgblack@eecs.umich.edu } 2106138Sgblack@eecs.umich.edu intPort->sendMessage(apics, message, 2116138Sgblack@eecs.umich.edu sys->getMemoryMode() == Enums::timing); 2125643Sgblack@eecs.umich.edu } 2135643Sgblack@eecs.umich.edu} 2145643Sgblack@eecs.umich.edu 2155827Sgblack@eecs.umich.eduvoid 2165827Sgblack@eecs.umich.eduX86ISA::I82094AA::raiseInterruptPin(int number) 2175827Sgblack@eecs.umich.edu{ 2185827Sgblack@eecs.umich.edu assert(number < TableSize); 2195827Sgblack@eecs.umich.edu if (!pinStates[number]) 2205827Sgblack@eecs.umich.edu signalInterrupt(number); 2215827Sgblack@eecs.umich.edu pinStates[number] = true; 2225827Sgblack@eecs.umich.edu} 2235827Sgblack@eecs.umich.edu 2245827Sgblack@eecs.umich.eduvoid 2255827Sgblack@eecs.umich.eduX86ISA::I82094AA::lowerInterruptPin(int number) 2265827Sgblack@eecs.umich.edu{ 2275827Sgblack@eecs.umich.edu assert(number < TableSize); 2285827Sgblack@eecs.umich.edu pinStates[number] = false; 2295827Sgblack@eecs.umich.edu} 2305827Sgblack@eecs.umich.edu 2316137Sgblack@eecs.umich.eduvoid 2326137Sgblack@eecs.umich.eduX86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic) 2336137Sgblack@eecs.umich.edu{ 2346137Sgblack@eecs.umich.edu assert(localApic); 2356137Sgblack@eecs.umich.edu localApics[initialId] = localApic; 2366137Sgblack@eecs.umich.edu} 2376137Sgblack@eecs.umich.edu 2385643Sgblack@eecs.umich.eduX86ISA::I82094AA * 2395643Sgblack@eecs.umich.eduI82094AAParams::create() 2405643Sgblack@eecs.umich.edu{ 2415643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 2425643Sgblack@eecs.umich.edu} 243