i82094aa.cc revision 5827
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 315651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 325643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 335657Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 345643Sgblack@eecs.umich.edu#include "mem/packet.hh" 355643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 365643Sgblack@eecs.umich.edu#include "sim/system.hh" 375643Sgblack@eecs.umich.edu 385651Sgblack@eecs.umich.eduX86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), 395827Sgblack@eecs.umich.edu latency(p->pio_latency), pioAddr(p->pio_addr), 405827Sgblack@eecs.umich.edu extIntPic(p->external_int_pic) 415643Sgblack@eecs.umich.edu{ 425643Sgblack@eecs.umich.edu // This assumes there's only one I/O APIC in the system 435720Snate@binkert.org id = sys->numContexts(); 445643Sgblack@eecs.umich.edu assert(id <= 0xf); 455643Sgblack@eecs.umich.edu arbId = id; 465643Sgblack@eecs.umich.edu regSel = 0; 475653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 485653Sgblack@eecs.umich.edu entry.mask = 1; 495653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 505653Sgblack@eecs.umich.edu redirTable[i] = entry; 515827Sgblack@eecs.umich.edu pinStates[i] = false; 525653Sgblack@eecs.umich.edu } 535643Sgblack@eecs.umich.edu} 545643Sgblack@eecs.umich.edu 555643Sgblack@eecs.umich.eduTick 565643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 575643Sgblack@eecs.umich.edu{ 585643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 595643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 605643Sgblack@eecs.umich.edu switch(offset) { 615643Sgblack@eecs.umich.edu case 0: 625643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 635643Sgblack@eecs.umich.edu break; 645643Sgblack@eecs.umich.edu case 16: 655643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 665643Sgblack@eecs.umich.edu break; 675643Sgblack@eecs.umich.edu default: 685643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 695643Sgblack@eecs.umich.edu } 705643Sgblack@eecs.umich.edu return latency; 715643Sgblack@eecs.umich.edu} 725643Sgblack@eecs.umich.edu 735643Sgblack@eecs.umich.eduTick 745643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 755643Sgblack@eecs.umich.edu{ 765643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 775643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 785643Sgblack@eecs.umich.edu switch(offset) { 795643Sgblack@eecs.umich.edu case 0: 805643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 815643Sgblack@eecs.umich.edu break; 825643Sgblack@eecs.umich.edu case 16: 835643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 845643Sgblack@eecs.umich.edu break; 855643Sgblack@eecs.umich.edu default: 865643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 875643Sgblack@eecs.umich.edu } 885643Sgblack@eecs.umich.edu return latency; 895643Sgblack@eecs.umich.edu} 905643Sgblack@eecs.umich.edu 915643Sgblack@eecs.umich.eduvoid 925643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 935643Sgblack@eecs.umich.edu{ 945643Sgblack@eecs.umich.edu if (offset == 0x0) { 955643Sgblack@eecs.umich.edu id = bits(value, 27, 24); 965643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 975643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 985643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 995643Sgblack@eecs.umich.edu arbId = bits(value, 27, 24); 1005643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1015643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1025643Sgblack@eecs.umich.edu if (offset % 2) { 1035643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1045643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1055643Sgblack@eecs.umich.edu } else { 1065643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1075643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1085643Sgblack@eecs.umich.edu } 1095643Sgblack@eecs.umich.edu } else { 1105643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1115643Sgblack@eecs.umich.edu } 1125643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1135643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1145643Sgblack@eecs.umich.edu} 1155643Sgblack@eecs.umich.edu 1165643Sgblack@eecs.umich.eduuint32_t 1175643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1185643Sgblack@eecs.umich.edu{ 1195643Sgblack@eecs.umich.edu uint32_t result = 0; 1205643Sgblack@eecs.umich.edu if (offset == 0x0) { 1215643Sgblack@eecs.umich.edu result = id << 24; 1225643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1235643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1245643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1255643Sgblack@eecs.umich.edu result = arbId << 24; 1265643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1275643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1285643Sgblack@eecs.umich.edu if (offset % 2) { 1295643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1305643Sgblack@eecs.umich.edu } else { 1315643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1325643Sgblack@eecs.umich.edu } 1335643Sgblack@eecs.umich.edu } else { 1345643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1355643Sgblack@eecs.umich.edu } 1365643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1375643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1385643Sgblack@eecs.umich.edu return result; 1395643Sgblack@eecs.umich.edu} 1405643Sgblack@eecs.umich.edu 1415643Sgblack@eecs.umich.eduvoid 1425643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1435643Sgblack@eecs.umich.edu{ 1445643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1455643Sgblack@eecs.umich.edu assert(line < TableSize); 1465643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1475643Sgblack@eecs.umich.edu if (entry.mask) { 1485643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1495643Sgblack@eecs.umich.edu return; 1505643Sgblack@eecs.umich.edu } else { 1515651Sgblack@eecs.umich.edu TriggerIntMessage message; 1525651Sgblack@eecs.umich.edu message.destination = entry.dest; 1535657Sgblack@eecs.umich.edu if (entry.deliveryMode == DeliveryMode::ExtInt) { 1545657Sgblack@eecs.umich.edu assert(extIntPic); 1555657Sgblack@eecs.umich.edu message.vector = extIntPic->getVector(); 1565657Sgblack@eecs.umich.edu } else { 1575657Sgblack@eecs.umich.edu message.vector = entry.vector; 1585657Sgblack@eecs.umich.edu } 1595651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 1605651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 1615654Sgblack@eecs.umich.edu message.level = entry.polarity; 1625654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 1635651Sgblack@eecs.umich.edu 1645657Sgblack@eecs.umich.edu if (DeliveryMode::isReserved(entry.deliveryMode)) { 1655657Sgblack@eecs.umich.edu fatal("Tried to use reserved delivery mode " 1665657Sgblack@eecs.umich.edu "for IO APIC entry %d.\n", line); 1675657Sgblack@eecs.umich.edu } else if (DTRACE(I82094AA)) { 1685657Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: %s.\n", 1695657Sgblack@eecs.umich.edu DeliveryMode::names[entry.deliveryMode]); 1705657Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Vector is %#x.\n", message.vector); 1715657Sgblack@eecs.umich.edu } 1725657Sgblack@eecs.umich.edu 1735643Sgblack@eecs.umich.edu if (entry.destMode == 0) { 1745643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1755651Sgblack@eecs.umich.edu "Sending interrupt to APIC ID %d.\n", entry.dest); 1765651Sgblack@eecs.umich.edu PacketPtr pkt = buildIntRequest(entry.dest, message); 1775651Sgblack@eecs.umich.edu if (sys->getMemoryMode() == Enums::timing) 1785651Sgblack@eecs.umich.edu intPort->sendMessageTiming(pkt, latency); 1795651Sgblack@eecs.umich.edu else if (sys->getMemoryMode() == Enums::atomic) 1805651Sgblack@eecs.umich.edu intPort->sendMessageAtomic(pkt); 1815651Sgblack@eecs.umich.edu else 1825651Sgblack@eecs.umich.edu panic("Unrecognized memory mode.\n"); 1835643Sgblack@eecs.umich.edu } else { 1845651Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Sending interrupts to APIC IDs:" 1855643Sgblack@eecs.umich.edu "%s%s%s%s%s%s%s%s\n", 1865643Sgblack@eecs.umich.edu bits((int)entry.dest, 0) ? " 0": "", 1875643Sgblack@eecs.umich.edu bits((int)entry.dest, 1) ? " 1": "", 1885643Sgblack@eecs.umich.edu bits((int)entry.dest, 2) ? " 2": "", 1895643Sgblack@eecs.umich.edu bits((int)entry.dest, 3) ? " 3": "", 1905643Sgblack@eecs.umich.edu bits((int)entry.dest, 4) ? " 4": "", 1915643Sgblack@eecs.umich.edu bits((int)entry.dest, 5) ? " 5": "", 1925643Sgblack@eecs.umich.edu bits((int)entry.dest, 6) ? " 6": "", 1935643Sgblack@eecs.umich.edu bits((int)entry.dest, 7) ? " 7": "" 1945643Sgblack@eecs.umich.edu ); 1955651Sgblack@eecs.umich.edu uint8_t dests = entry.dest; 1965651Sgblack@eecs.umich.edu uint8_t id = 0; 1975651Sgblack@eecs.umich.edu while(dests) { 1985651Sgblack@eecs.umich.edu if (dests & 0x1) { 1995651Sgblack@eecs.umich.edu PacketPtr pkt = buildIntRequest(id, message); 2005651Sgblack@eecs.umich.edu if (sys->getMemoryMode() == Enums::timing) 2015651Sgblack@eecs.umich.edu intPort->sendMessageTiming(pkt, latency); 2025651Sgblack@eecs.umich.edu else if (sys->getMemoryMode() == Enums::atomic) 2035651Sgblack@eecs.umich.edu intPort->sendMessageAtomic(pkt); 2045651Sgblack@eecs.umich.edu else 2055651Sgblack@eecs.umich.edu panic("Unrecognized memory mode.\n"); 2065651Sgblack@eecs.umich.edu } 2075651Sgblack@eecs.umich.edu dests >>= 1; 2085651Sgblack@eecs.umich.edu id++; 2095651Sgblack@eecs.umich.edu } 2105643Sgblack@eecs.umich.edu } 2115643Sgblack@eecs.umich.edu } 2125643Sgblack@eecs.umich.edu} 2135643Sgblack@eecs.umich.edu 2145827Sgblack@eecs.umich.eduvoid 2155827Sgblack@eecs.umich.eduX86ISA::I82094AA::raiseInterruptPin(int number) 2165827Sgblack@eecs.umich.edu{ 2175827Sgblack@eecs.umich.edu assert(number < TableSize); 2185827Sgblack@eecs.umich.edu if (!pinStates[number]) 2195827Sgblack@eecs.umich.edu signalInterrupt(number); 2205827Sgblack@eecs.umich.edu pinStates[number] = true; 2215827Sgblack@eecs.umich.edu} 2225827Sgblack@eecs.umich.edu 2235827Sgblack@eecs.umich.eduvoid 2245827Sgblack@eecs.umich.eduX86ISA::I82094AA::lowerInterruptPin(int number) 2255827Sgblack@eecs.umich.edu{ 2265827Sgblack@eecs.umich.edu assert(number < TableSize); 2275827Sgblack@eecs.umich.edu pinStates[number] = false; 2285827Sgblack@eecs.umich.edu} 2295827Sgblack@eecs.umich.edu 2305643Sgblack@eecs.umich.eduX86ISA::I82094AA * 2315643Sgblack@eecs.umich.eduI82094AAParams::create() 2325643Sgblack@eecs.umich.edu{ 2335643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 2345643Sgblack@eecs.umich.edu} 235