i82094aa.cc revision 5654
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 315651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 325643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 335643Sgblack@eecs.umich.edu#include "mem/packet.hh" 345643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 355643Sgblack@eecs.umich.edu#include "sim/system.hh" 365643Sgblack@eecs.umich.edu 375651Sgblack@eecs.umich.eduX86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), 385643Sgblack@eecs.umich.edu latency(p->pio_latency), pioAddr(p->pio_addr) 395643Sgblack@eecs.umich.edu{ 405643Sgblack@eecs.umich.edu // This assumes there's only one I/O APIC in the system 415643Sgblack@eecs.umich.edu id = sys->getNumCPUs(); 425643Sgblack@eecs.umich.edu assert(id <= 0xf); 435643Sgblack@eecs.umich.edu arbId = id; 445643Sgblack@eecs.umich.edu regSel = 0; 455653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 465653Sgblack@eecs.umich.edu entry.mask = 1; 475653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 485653Sgblack@eecs.umich.edu redirTable[i] = entry; 495653Sgblack@eecs.umich.edu } 505643Sgblack@eecs.umich.edu} 515643Sgblack@eecs.umich.edu 525643Sgblack@eecs.umich.eduTick 535643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 545643Sgblack@eecs.umich.edu{ 555643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 565643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 575643Sgblack@eecs.umich.edu switch(offset) { 585643Sgblack@eecs.umich.edu case 0: 595643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 605643Sgblack@eecs.umich.edu break; 615643Sgblack@eecs.umich.edu case 16: 625643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 635643Sgblack@eecs.umich.edu break; 645643Sgblack@eecs.umich.edu default: 655643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 665643Sgblack@eecs.umich.edu } 675643Sgblack@eecs.umich.edu return latency; 685643Sgblack@eecs.umich.edu} 695643Sgblack@eecs.umich.edu 705643Sgblack@eecs.umich.eduTick 715643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 725643Sgblack@eecs.umich.edu{ 735643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 745643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 755643Sgblack@eecs.umich.edu switch(offset) { 765643Sgblack@eecs.umich.edu case 0: 775643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 785643Sgblack@eecs.umich.edu break; 795643Sgblack@eecs.umich.edu case 16: 805643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 815643Sgblack@eecs.umich.edu break; 825643Sgblack@eecs.umich.edu default: 835643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 845643Sgblack@eecs.umich.edu } 855643Sgblack@eecs.umich.edu return latency; 865643Sgblack@eecs.umich.edu} 875643Sgblack@eecs.umich.edu 885643Sgblack@eecs.umich.eduvoid 895643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 905643Sgblack@eecs.umich.edu{ 915643Sgblack@eecs.umich.edu if (offset == 0x0) { 925643Sgblack@eecs.umich.edu id = bits(value, 27, 24); 935643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 945643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 955643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 965643Sgblack@eecs.umich.edu arbId = bits(value, 27, 24); 975643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 985643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 995643Sgblack@eecs.umich.edu if (offset % 2) { 1005643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1015643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1025643Sgblack@eecs.umich.edu } else { 1035643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1045643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1055643Sgblack@eecs.umich.edu } 1065643Sgblack@eecs.umich.edu } else { 1075643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1085643Sgblack@eecs.umich.edu } 1095643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1105643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1115643Sgblack@eecs.umich.edu} 1125643Sgblack@eecs.umich.edu 1135643Sgblack@eecs.umich.eduuint32_t 1145643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1155643Sgblack@eecs.umich.edu{ 1165643Sgblack@eecs.umich.edu uint32_t result = 0; 1175643Sgblack@eecs.umich.edu if (offset == 0x0) { 1185643Sgblack@eecs.umich.edu result = id << 24; 1195643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1205643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1215643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1225643Sgblack@eecs.umich.edu result = arbId << 24; 1235643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1245643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1255643Sgblack@eecs.umich.edu if (offset % 2) { 1265643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1275643Sgblack@eecs.umich.edu } else { 1285643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1295643Sgblack@eecs.umich.edu } 1305643Sgblack@eecs.umich.edu } else { 1315643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1325643Sgblack@eecs.umich.edu } 1335643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1345643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1355643Sgblack@eecs.umich.edu return result; 1365643Sgblack@eecs.umich.edu} 1375643Sgblack@eecs.umich.edu 1385643Sgblack@eecs.umich.eduvoid 1395643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1405643Sgblack@eecs.umich.edu{ 1415643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1425643Sgblack@eecs.umich.edu assert(line < TableSize); 1435643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1445643Sgblack@eecs.umich.edu if (entry.mask) { 1455643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1465643Sgblack@eecs.umich.edu return; 1475643Sgblack@eecs.umich.edu } else { 1485651Sgblack@eecs.umich.edu if (DTRACE(I82094AA)) { 1495654Sgblack@eecs.umich.edu if (DeliveryMode::isReserved(entry.deliveryMode)) { 1505651Sgblack@eecs.umich.edu fatal("Tried to use reserved delivery mode " 1515651Sgblack@eecs.umich.edu "for IO APIC entry %d.\n", line); 1525654Sgblack@eecs.umich.edu } else { 1535654Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: %s.\n", 1545654Sgblack@eecs.umich.edu DeliveryMode::names[entry.deliveryMode]); 1555651Sgblack@eecs.umich.edu } 1565651Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector); 1575651Sgblack@eecs.umich.edu } 1585651Sgblack@eecs.umich.edu 1595651Sgblack@eecs.umich.edu TriggerIntMessage message; 1605651Sgblack@eecs.umich.edu message.destination = entry.dest; 1615651Sgblack@eecs.umich.edu message.vector = entry.vector; 1625651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 1635651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 1645654Sgblack@eecs.umich.edu message.level = entry.polarity; 1655654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 1665651Sgblack@eecs.umich.edu 1675643Sgblack@eecs.umich.edu if (entry.destMode == 0) { 1685643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1695651Sgblack@eecs.umich.edu "Sending interrupt to APIC ID %d.\n", entry.dest); 1705651Sgblack@eecs.umich.edu PacketPtr pkt = buildIntRequest(entry.dest, message); 1715651Sgblack@eecs.umich.edu if (sys->getMemoryMode() == Enums::timing) 1725651Sgblack@eecs.umich.edu intPort->sendMessageTiming(pkt, latency); 1735651Sgblack@eecs.umich.edu else if (sys->getMemoryMode() == Enums::atomic) 1745651Sgblack@eecs.umich.edu intPort->sendMessageAtomic(pkt); 1755651Sgblack@eecs.umich.edu else 1765651Sgblack@eecs.umich.edu panic("Unrecognized memory mode.\n"); 1775643Sgblack@eecs.umich.edu } else { 1785651Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Sending interrupts to APIC IDs:" 1795643Sgblack@eecs.umich.edu "%s%s%s%s%s%s%s%s\n", 1805643Sgblack@eecs.umich.edu bits((int)entry.dest, 0) ? " 0": "", 1815643Sgblack@eecs.umich.edu bits((int)entry.dest, 1) ? " 1": "", 1825643Sgblack@eecs.umich.edu bits((int)entry.dest, 2) ? " 2": "", 1835643Sgblack@eecs.umich.edu bits((int)entry.dest, 3) ? " 3": "", 1845643Sgblack@eecs.umich.edu bits((int)entry.dest, 4) ? " 4": "", 1855643Sgblack@eecs.umich.edu bits((int)entry.dest, 5) ? " 5": "", 1865643Sgblack@eecs.umich.edu bits((int)entry.dest, 6) ? " 6": "", 1875643Sgblack@eecs.umich.edu bits((int)entry.dest, 7) ? " 7": "" 1885643Sgblack@eecs.umich.edu ); 1895651Sgblack@eecs.umich.edu uint8_t dests = entry.dest; 1905651Sgblack@eecs.umich.edu uint8_t id = 0; 1915651Sgblack@eecs.umich.edu while(dests) { 1925651Sgblack@eecs.umich.edu if (dests & 0x1) { 1935651Sgblack@eecs.umich.edu PacketPtr pkt = buildIntRequest(id, message); 1945651Sgblack@eecs.umich.edu if (sys->getMemoryMode() == Enums::timing) 1955651Sgblack@eecs.umich.edu intPort->sendMessageTiming(pkt, latency); 1965651Sgblack@eecs.umich.edu else if (sys->getMemoryMode() == Enums::atomic) 1975651Sgblack@eecs.umich.edu intPort->sendMessageAtomic(pkt); 1985651Sgblack@eecs.umich.edu else 1995651Sgblack@eecs.umich.edu panic("Unrecognized memory mode.\n"); 2005651Sgblack@eecs.umich.edu } 2015651Sgblack@eecs.umich.edu dests >>= 1; 2025651Sgblack@eecs.umich.edu id++; 2035651Sgblack@eecs.umich.edu } 2045643Sgblack@eecs.umich.edu } 2055643Sgblack@eecs.umich.edu } 2065643Sgblack@eecs.umich.edu} 2075643Sgblack@eecs.umich.edu 2085643Sgblack@eecs.umich.eduX86ISA::I82094AA * 2095643Sgblack@eecs.umich.eduI82094AAParams::create() 2105643Sgblack@eecs.umich.edu{ 2115643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 2125643Sgblack@eecs.umich.edu} 213