i82094aa.cc revision 14291
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 3111793Sbrandon.potter@amd.com#include "dev/x86/i82094aa.hh" 3211793Sbrandon.potter@amd.com 336138Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 345651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 358746Sgblack@eecs.umich.edu#include "cpu/base.hh" 368232Snate@binkert.org#include "debug/I82094AA.hh" 375657Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 385643Sgblack@eecs.umich.edu#include "mem/packet.hh" 395643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 405643Sgblack@eecs.umich.edu#include "sim/system.hh" 415643Sgblack@eecs.umich.edu 429805Sstever@gmail.comX86ISA::I82094AA::I82094AA(Params *p) 439808Sstever@gmail.com : BasicPioDevice(p, 20), IntDevice(this, p->int_latency), 449805Sstever@gmail.com extIntPic(p->external_int_pic), lowestPriorityOffset(0) 455643Sgblack@eecs.umich.edu{ 467913SBrad.Beckmann@amd.com // This assumes there's only one I/O APIC in the system and since the apic 477913SBrad.Beckmann@amd.com // id is stored in a 8-bit field with 0xff meaning broadcast, the id must 487913SBrad.Beckmann@amd.com // be less than 0xff 497913SBrad.Beckmann@amd.com 507913SBrad.Beckmann@amd.com assert(p->apic_id < 0xff); 516136Sgblack@eecs.umich.edu initialApicId = id = p->apic_id; 525643Sgblack@eecs.umich.edu arbId = id; 535643Sgblack@eecs.umich.edu regSel = 0; 545653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 555653Sgblack@eecs.umich.edu entry.mask = 1; 565653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 575653Sgblack@eecs.umich.edu redirTable[i] = entry; 585827Sgblack@eecs.umich.edu pinStates[i] = false; 595653Sgblack@eecs.umich.edu } 6014290Sgabeblack@google.com 6114290Sgabeblack@google.com for (int i = 0; i < p->port_inputs_connection_count; i++) 6214291Sgabeblack@google.com inputs.push_back(new IntSinkPin<I82094AA>( 6314290Sgabeblack@google.com csprintf("%s.inputs[%d]", name(), i), i, this)); 645643Sgblack@eecs.umich.edu} 655643Sgblack@eecs.umich.edu 667913SBrad.Beckmann@amd.comvoid 677913SBrad.Beckmann@amd.comX86ISA::I82094AA::init() 687913SBrad.Beckmann@amd.com{ 697913SBrad.Beckmann@amd.com // The io apic must register its address ranges on both its pio port 707913SBrad.Beckmann@amd.com // via the piodevice init() function and its int port that it inherited 719807Sstever@gmail.com // from IntDevice. Note IntDevice is not a SimObject itself. 727913SBrad.Beckmann@amd.com 739805Sstever@gmail.com BasicPioDevice::init(); 749807Sstever@gmail.com IntDevice::init(); 757913SBrad.Beckmann@amd.com} 767913SBrad.Beckmann@amd.com 7713784Sgabeblack@google.comPort & 7813784Sgabeblack@google.comX86ISA::I82094AA::getPort(const std::string &if_name, PortID idx) 799805Sstever@gmail.com{ 809805Sstever@gmail.com if (if_name == "int_master") 819805Sstever@gmail.com return intMasterPort; 8214290Sgabeblack@google.com if (if_name == "inputs") 8314290Sgabeblack@google.com return *inputs.at(idx); 8414290Sgabeblack@google.com else 8514290Sgabeblack@google.com return BasicPioDevice::getPort(if_name, idx); 869805Sstever@gmail.com} 879805Sstever@gmail.com 889805Sstever@gmail.comAddrRangeList 899805Sstever@gmail.comX86ISA::I82094AA::getIntAddrRange() const 909805Sstever@gmail.com{ 919805Sstever@gmail.com AddrRangeList ranges; 929805Sstever@gmail.com ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 939805Sstever@gmail.com x86InterruptAddress(initialApicId, 0) + 949805Sstever@gmail.com PhysAddrAPICRangeSize)); 959805Sstever@gmail.com return ranges; 969805Sstever@gmail.com} 979805Sstever@gmail.com 985643Sgblack@eecs.umich.eduTick 9911144Sjthestness@gmail.comX86ISA::I82094AA::recvResponse(PacketPtr pkt) 10011144Sjthestness@gmail.com{ 10111144Sjthestness@gmail.com // Packet instantiated calling sendMessage() in signalInterrupt() 10211144Sjthestness@gmail.com delete pkt; 10311144Sjthestness@gmail.com return 0; 10411144Sjthestness@gmail.com} 10511144Sjthestness@gmail.com 10611144Sjthestness@gmail.comTick 1075643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 1085643Sgblack@eecs.umich.edu{ 1095643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 1105643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 1115643Sgblack@eecs.umich.edu switch(offset) { 1125643Sgblack@eecs.umich.edu case 0: 11313229Sgabeblack@google.com pkt->setLE<uint32_t>(regSel); 1145643Sgblack@eecs.umich.edu break; 1155643Sgblack@eecs.umich.edu case 16: 11613229Sgabeblack@google.com pkt->setLE<uint32_t>(readReg(regSel)); 1175643Sgblack@eecs.umich.edu break; 1185643Sgblack@eecs.umich.edu default: 1195643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 1205643Sgblack@eecs.umich.edu } 1215898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 1229805Sstever@gmail.com return pioDelay; 1235643Sgblack@eecs.umich.edu} 1245643Sgblack@eecs.umich.edu 1255643Sgblack@eecs.umich.eduTick 1265643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 1275643Sgblack@eecs.umich.edu{ 1285643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 1295643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 1305643Sgblack@eecs.umich.edu switch(offset) { 1315643Sgblack@eecs.umich.edu case 0: 13213229Sgabeblack@google.com regSel = pkt->getLE<uint32_t>(); 1335643Sgblack@eecs.umich.edu break; 1345643Sgblack@eecs.umich.edu case 16: 13513229Sgabeblack@google.com writeReg(regSel, pkt->getLE<uint32_t>()); 1365643Sgblack@eecs.umich.edu break; 1375643Sgblack@eecs.umich.edu default: 1385643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 1395643Sgblack@eecs.umich.edu } 1405898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 1419805Sstever@gmail.com return pioDelay; 1425643Sgblack@eecs.umich.edu} 1435643Sgblack@eecs.umich.edu 1445643Sgblack@eecs.umich.eduvoid 1455643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 1465643Sgblack@eecs.umich.edu{ 1475643Sgblack@eecs.umich.edu if (offset == 0x0) { 1487913SBrad.Beckmann@amd.com id = bits(value, 31, 24); 1495643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1505643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 1515643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1527913SBrad.Beckmann@amd.com arbId = bits(value, 31, 24); 1535643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1545643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1555643Sgblack@eecs.umich.edu if (offset % 2) { 1565643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1575643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1585643Sgblack@eecs.umich.edu } else { 1595643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1605643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1615643Sgblack@eecs.umich.edu } 1625643Sgblack@eecs.umich.edu } else { 1635643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1645643Sgblack@eecs.umich.edu } 1655643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1665643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1675643Sgblack@eecs.umich.edu} 1685643Sgblack@eecs.umich.edu 1695643Sgblack@eecs.umich.eduuint32_t 1705643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1715643Sgblack@eecs.umich.edu{ 1725643Sgblack@eecs.umich.edu uint32_t result = 0; 1735643Sgblack@eecs.umich.edu if (offset == 0x0) { 1745643Sgblack@eecs.umich.edu result = id << 24; 1755643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1765643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1775643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1785643Sgblack@eecs.umich.edu result = arbId << 24; 1795643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1805643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1815643Sgblack@eecs.umich.edu if (offset % 2) { 1825643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1835643Sgblack@eecs.umich.edu } else { 1845643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1855643Sgblack@eecs.umich.edu } 1865643Sgblack@eecs.umich.edu } else { 1875643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1885643Sgblack@eecs.umich.edu } 1895643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1905643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1915643Sgblack@eecs.umich.edu return result; 1925643Sgblack@eecs.umich.edu} 1935643Sgblack@eecs.umich.edu 1945643Sgblack@eecs.umich.eduvoid 1955643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1965643Sgblack@eecs.umich.edu{ 1975643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1985643Sgblack@eecs.umich.edu assert(line < TableSize); 1995643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 2005643Sgblack@eecs.umich.edu if (entry.mask) { 2015643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 2025643Sgblack@eecs.umich.edu return; 2035643Sgblack@eecs.umich.edu } else { 2046712Snate@binkert.org TriggerIntMessage message = 0; 2055651Sgblack@eecs.umich.edu message.destination = entry.dest; 2065657Sgblack@eecs.umich.edu if (entry.deliveryMode == DeliveryMode::ExtInt) { 2075657Sgblack@eecs.umich.edu assert(extIntPic); 2085657Sgblack@eecs.umich.edu message.vector = extIntPic->getVector(); 2095657Sgblack@eecs.umich.edu } else { 2105657Sgblack@eecs.umich.edu message.vector = entry.vector; 2115657Sgblack@eecs.umich.edu } 2125651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 2135651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 2145654Sgblack@eecs.umich.edu message.level = entry.polarity; 2155654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 2166138Sgblack@eecs.umich.edu ApicList apics; 2176138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 2186138Sgblack@eecs.umich.edu if (message.destMode == 0) { 2196138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 2206138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode from the " 2216138Sgblack@eecs.umich.edu "IO APIC aren't supported in physical " 2226138Sgblack@eecs.umich.edu "destination mode.\n"); 2236138Sgblack@eecs.umich.edu } 2246138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 2256138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 2266138Sgblack@eecs.umich.edu apics.push_back(i); 2276138Sgblack@eecs.umich.edu } 2286138Sgblack@eecs.umich.edu } else { 2296138Sgblack@eecs.umich.edu apics.push_back(message.destination); 2306138Sgblack@eecs.umich.edu } 2316138Sgblack@eecs.umich.edu } else { 2326138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 2338746Sgblack@eecs.umich.edu Interrupts *localApic = sys->getThreadContext(i)-> 23411150Smitch.hayenga@arm.com getCpuPtr()->getInterruptController(0); 2356138Sgblack@eecs.umich.edu if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 2366138Sgblack@eecs.umich.edu message.destination) { 2378746Sgblack@eecs.umich.edu apics.push_back(localApic->getInitialApicId()); 2386138Sgblack@eecs.umich.edu } 2396138Sgblack@eecs.umich.edu } 2406139Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority && 2416139Sgblack@eecs.umich.edu apics.size()) { 2426139Sgblack@eecs.umich.edu // The manual seems to suggest that the chipset just does 2436139Sgblack@eecs.umich.edu // something reasonable for these instead of actually using 2446139Sgblack@eecs.umich.edu // state from the local APIC. We'll just rotate an offset 2456139Sgblack@eecs.umich.edu // through the set of APICs selected above. 2466139Sgblack@eecs.umich.edu uint64_t modOffset = lowestPriorityOffset % apics.size(); 2476139Sgblack@eecs.umich.edu lowestPriorityOffset++; 2486139Sgblack@eecs.umich.edu ApicList::iterator apicIt = apics.begin(); 2496139Sgblack@eecs.umich.edu while (modOffset--) { 2506139Sgblack@eecs.umich.edu apicIt++; 2516139Sgblack@eecs.umich.edu assert(apicIt != apics.end()); 2526139Sgblack@eecs.umich.edu } 2536139Sgblack@eecs.umich.edu int selected = *apicIt; 2546139Sgblack@eecs.umich.edu apics.clear(); 2556139Sgblack@eecs.umich.edu apics.push_back(selected); 2566138Sgblack@eecs.umich.edu } 2576138Sgblack@eecs.umich.edu } 2589524SAndreas.Sandberg@ARM.com intMasterPort.sendMessage(apics, message, sys->isTimingMode()); 2595643Sgblack@eecs.umich.edu } 2605643Sgblack@eecs.umich.edu} 2615643Sgblack@eecs.umich.edu 2625827Sgblack@eecs.umich.eduvoid 2635827Sgblack@eecs.umich.eduX86ISA::I82094AA::raiseInterruptPin(int number) 2645827Sgblack@eecs.umich.edu{ 2655827Sgblack@eecs.umich.edu assert(number < TableSize); 2665827Sgblack@eecs.umich.edu if (!pinStates[number]) 2675827Sgblack@eecs.umich.edu signalInterrupt(number); 2685827Sgblack@eecs.umich.edu pinStates[number] = true; 2695827Sgblack@eecs.umich.edu} 2705827Sgblack@eecs.umich.edu 2715827Sgblack@eecs.umich.eduvoid 2725827Sgblack@eecs.umich.eduX86ISA::I82094AA::lowerInterruptPin(int number) 2735827Sgblack@eecs.umich.edu{ 2745827Sgblack@eecs.umich.edu assert(number < TableSize); 2755827Sgblack@eecs.umich.edu pinStates[number] = false; 2765827Sgblack@eecs.umich.edu} 2775827Sgblack@eecs.umich.edu 2786137Sgblack@eecs.umich.eduvoid 27910905Sandreas.sandberg@arm.comX86ISA::I82094AA::serialize(CheckpointOut &cp) const 2807903Shestness@cs.utexas.edu{ 2817903Shestness@cs.utexas.edu uint64_t* redirTableArray = (uint64_t*)redirTable; 2827903Shestness@cs.utexas.edu SERIALIZE_SCALAR(regSel); 2837903Shestness@cs.utexas.edu SERIALIZE_SCALAR(initialApicId); 2847903Shestness@cs.utexas.edu SERIALIZE_SCALAR(id); 2857903Shestness@cs.utexas.edu SERIALIZE_SCALAR(arbId); 2867903Shestness@cs.utexas.edu SERIALIZE_SCALAR(lowestPriorityOffset); 2877903Shestness@cs.utexas.edu SERIALIZE_ARRAY(redirTableArray, TableSize); 2887903Shestness@cs.utexas.edu SERIALIZE_ARRAY(pinStates, TableSize); 2897903Shestness@cs.utexas.edu} 2907903Shestness@cs.utexas.edu 2917903Shestness@cs.utexas.eduvoid 29210905Sandreas.sandberg@arm.comX86ISA::I82094AA::unserialize(CheckpointIn &cp) 2937903Shestness@cs.utexas.edu{ 2947903Shestness@cs.utexas.edu uint64_t redirTableArray[TableSize]; 2957903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(regSel); 2967903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initialApicId); 2977903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(id); 2987903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(arbId); 2997903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(lowestPriorityOffset); 3007903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(redirTableArray, TableSize); 3017903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(pinStates, TableSize); 3027903Shestness@cs.utexas.edu for (int i = 0; i < TableSize; i++) { 3037903Shestness@cs.utexas.edu redirTable[i] = (RedirTableEntry)redirTableArray[i]; 3047903Shestness@cs.utexas.edu } 3057903Shestness@cs.utexas.edu} 3067903Shestness@cs.utexas.edu 3075643Sgblack@eecs.umich.eduX86ISA::I82094AA * 3085643Sgblack@eecs.umich.eduI82094AAParams::create() 3095643Sgblack@eecs.umich.edu{ 3105643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 3115643Sgblack@eecs.umich.edu} 312