i82094aa.cc revision 11150
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 316138Sgblack@eecs.umich.edu#include "arch/x86/interrupts.hh" 325651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 338746Sgblack@eecs.umich.edu#include "cpu/base.hh" 348232Snate@binkert.org#include "debug/I82094AA.hh" 355643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 365657Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 375643Sgblack@eecs.umich.edu#include "mem/packet.hh" 385643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 395643Sgblack@eecs.umich.edu#include "sim/system.hh" 405643Sgblack@eecs.umich.edu 419805Sstever@gmail.comX86ISA::I82094AA::I82094AA(Params *p) 429808Sstever@gmail.com : BasicPioDevice(p, 20), IntDevice(this, p->int_latency), 439805Sstever@gmail.com extIntPic(p->external_int_pic), lowestPriorityOffset(0) 445643Sgblack@eecs.umich.edu{ 457913SBrad.Beckmann@amd.com // This assumes there's only one I/O APIC in the system and since the apic 467913SBrad.Beckmann@amd.com // id is stored in a 8-bit field with 0xff meaning broadcast, the id must 477913SBrad.Beckmann@amd.com // be less than 0xff 487913SBrad.Beckmann@amd.com 497913SBrad.Beckmann@amd.com assert(p->apic_id < 0xff); 506136Sgblack@eecs.umich.edu initialApicId = id = p->apic_id; 515643Sgblack@eecs.umich.edu arbId = id; 525643Sgblack@eecs.umich.edu regSel = 0; 535653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 545653Sgblack@eecs.umich.edu entry.mask = 1; 555653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 565653Sgblack@eecs.umich.edu redirTable[i] = entry; 575827Sgblack@eecs.umich.edu pinStates[i] = false; 585653Sgblack@eecs.umich.edu } 595643Sgblack@eecs.umich.edu} 605643Sgblack@eecs.umich.edu 617913SBrad.Beckmann@amd.comvoid 627913SBrad.Beckmann@amd.comX86ISA::I82094AA::init() 637913SBrad.Beckmann@amd.com{ 647913SBrad.Beckmann@amd.com // The io apic must register its address ranges on both its pio port 657913SBrad.Beckmann@amd.com // via the piodevice init() function and its int port that it inherited 669807Sstever@gmail.com // from IntDevice. Note IntDevice is not a SimObject itself. 677913SBrad.Beckmann@amd.com 689805Sstever@gmail.com BasicPioDevice::init(); 699807Sstever@gmail.com IntDevice::init(); 707913SBrad.Beckmann@amd.com} 717913SBrad.Beckmann@amd.com 729805Sstever@gmail.comBaseMasterPort & 739805Sstever@gmail.comX86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx) 749805Sstever@gmail.com{ 759805Sstever@gmail.com if (if_name == "int_master") 769805Sstever@gmail.com return intMasterPort; 779805Sstever@gmail.com return BasicPioDevice::getMasterPort(if_name, idx); 789805Sstever@gmail.com} 799805Sstever@gmail.com 809805Sstever@gmail.comAddrRangeList 819805Sstever@gmail.comX86ISA::I82094AA::getIntAddrRange() const 829805Sstever@gmail.com{ 839805Sstever@gmail.com AddrRangeList ranges; 849805Sstever@gmail.com ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0), 859805Sstever@gmail.com x86InterruptAddress(initialApicId, 0) + 869805Sstever@gmail.com PhysAddrAPICRangeSize)); 879805Sstever@gmail.com return ranges; 889805Sstever@gmail.com} 899805Sstever@gmail.com 905643Sgblack@eecs.umich.eduTick 9111144Sjthestness@gmail.comX86ISA::I82094AA::recvResponse(PacketPtr pkt) 9211144Sjthestness@gmail.com{ 9311144Sjthestness@gmail.com // Packet instantiated calling sendMessage() in signalInterrupt() 9411144Sjthestness@gmail.com delete pkt->req; 9511144Sjthestness@gmail.com delete pkt; 9611144Sjthestness@gmail.com return 0; 9711144Sjthestness@gmail.com} 9811144Sjthestness@gmail.com 9911144Sjthestness@gmail.comTick 1005643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 1015643Sgblack@eecs.umich.edu{ 1025643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 1035643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 1045643Sgblack@eecs.umich.edu switch(offset) { 1055643Sgblack@eecs.umich.edu case 0: 1065643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 1075643Sgblack@eecs.umich.edu break; 1085643Sgblack@eecs.umich.edu case 16: 1095643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 1105643Sgblack@eecs.umich.edu break; 1115643Sgblack@eecs.umich.edu default: 1125643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 1135643Sgblack@eecs.umich.edu } 1145898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 1159805Sstever@gmail.com return pioDelay; 1165643Sgblack@eecs.umich.edu} 1175643Sgblack@eecs.umich.edu 1185643Sgblack@eecs.umich.eduTick 1195643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 1205643Sgblack@eecs.umich.edu{ 1215643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 1225643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 1235643Sgblack@eecs.umich.edu switch(offset) { 1245643Sgblack@eecs.umich.edu case 0: 1255643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 1265643Sgblack@eecs.umich.edu break; 1275643Sgblack@eecs.umich.edu case 16: 1285643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 1295643Sgblack@eecs.umich.edu break; 1305643Sgblack@eecs.umich.edu default: 1315643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 1325643Sgblack@eecs.umich.edu } 1335898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 1349805Sstever@gmail.com return pioDelay; 1355643Sgblack@eecs.umich.edu} 1365643Sgblack@eecs.umich.edu 1375643Sgblack@eecs.umich.eduvoid 1385643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 1395643Sgblack@eecs.umich.edu{ 1405643Sgblack@eecs.umich.edu if (offset == 0x0) { 1417913SBrad.Beckmann@amd.com id = bits(value, 31, 24); 1425643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1435643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 1445643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1457913SBrad.Beckmann@amd.com arbId = bits(value, 31, 24); 1465643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1475643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1485643Sgblack@eecs.umich.edu if (offset % 2) { 1495643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1505643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1515643Sgblack@eecs.umich.edu } else { 1525643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1535643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1545643Sgblack@eecs.umich.edu } 1555643Sgblack@eecs.umich.edu } else { 1565643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1575643Sgblack@eecs.umich.edu } 1585643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1595643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1605643Sgblack@eecs.umich.edu} 1615643Sgblack@eecs.umich.edu 1625643Sgblack@eecs.umich.eduuint32_t 1635643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1645643Sgblack@eecs.umich.edu{ 1655643Sgblack@eecs.umich.edu uint32_t result = 0; 1665643Sgblack@eecs.umich.edu if (offset == 0x0) { 1675643Sgblack@eecs.umich.edu result = id << 24; 1685643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1695643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1705643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1715643Sgblack@eecs.umich.edu result = arbId << 24; 1725643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1735643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1745643Sgblack@eecs.umich.edu if (offset % 2) { 1755643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1765643Sgblack@eecs.umich.edu } else { 1775643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1785643Sgblack@eecs.umich.edu } 1795643Sgblack@eecs.umich.edu } else { 1805643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1815643Sgblack@eecs.umich.edu } 1825643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1835643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1845643Sgblack@eecs.umich.edu return result; 1855643Sgblack@eecs.umich.edu} 1865643Sgblack@eecs.umich.edu 1875643Sgblack@eecs.umich.eduvoid 1885643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1895643Sgblack@eecs.umich.edu{ 1905643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1915643Sgblack@eecs.umich.edu assert(line < TableSize); 1925643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1935643Sgblack@eecs.umich.edu if (entry.mask) { 1945643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1955643Sgblack@eecs.umich.edu return; 1965643Sgblack@eecs.umich.edu } else { 1976712Snate@binkert.org TriggerIntMessage message = 0; 1985651Sgblack@eecs.umich.edu message.destination = entry.dest; 1995657Sgblack@eecs.umich.edu if (entry.deliveryMode == DeliveryMode::ExtInt) { 2005657Sgblack@eecs.umich.edu assert(extIntPic); 2015657Sgblack@eecs.umich.edu message.vector = extIntPic->getVector(); 2025657Sgblack@eecs.umich.edu } else { 2035657Sgblack@eecs.umich.edu message.vector = entry.vector; 2045657Sgblack@eecs.umich.edu } 2055651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 2065651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 2075654Sgblack@eecs.umich.edu message.level = entry.polarity; 2085654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 2096138Sgblack@eecs.umich.edu ApicList apics; 2106138Sgblack@eecs.umich.edu int numContexts = sys->numContexts(); 2116138Sgblack@eecs.umich.edu if (message.destMode == 0) { 2126138Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority) { 2136138Sgblack@eecs.umich.edu panic("Lowest priority delivery mode from the " 2146138Sgblack@eecs.umich.edu "IO APIC aren't supported in physical " 2156138Sgblack@eecs.umich.edu "destination mode.\n"); 2166138Sgblack@eecs.umich.edu } 2176138Sgblack@eecs.umich.edu if (message.destination == 0xFF) { 2186138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 2196138Sgblack@eecs.umich.edu apics.push_back(i); 2206138Sgblack@eecs.umich.edu } 2216138Sgblack@eecs.umich.edu } else { 2226138Sgblack@eecs.umich.edu apics.push_back(message.destination); 2236138Sgblack@eecs.umich.edu } 2246138Sgblack@eecs.umich.edu } else { 2256138Sgblack@eecs.umich.edu for (int i = 0; i < numContexts; i++) { 2268746Sgblack@eecs.umich.edu Interrupts *localApic = sys->getThreadContext(i)-> 22711150Smitch.hayenga@arm.com getCpuPtr()->getInterruptController(0); 2286138Sgblack@eecs.umich.edu if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 2296138Sgblack@eecs.umich.edu message.destination) { 2308746Sgblack@eecs.umich.edu apics.push_back(localApic->getInitialApicId()); 2316138Sgblack@eecs.umich.edu } 2326138Sgblack@eecs.umich.edu } 2336139Sgblack@eecs.umich.edu if (message.deliveryMode == DeliveryMode::LowestPriority && 2346139Sgblack@eecs.umich.edu apics.size()) { 2356139Sgblack@eecs.umich.edu // The manual seems to suggest that the chipset just does 2366139Sgblack@eecs.umich.edu // something reasonable for these instead of actually using 2376139Sgblack@eecs.umich.edu // state from the local APIC. We'll just rotate an offset 2386139Sgblack@eecs.umich.edu // through the set of APICs selected above. 2396139Sgblack@eecs.umich.edu uint64_t modOffset = lowestPriorityOffset % apics.size(); 2406139Sgblack@eecs.umich.edu lowestPriorityOffset++; 2416139Sgblack@eecs.umich.edu ApicList::iterator apicIt = apics.begin(); 2426139Sgblack@eecs.umich.edu while (modOffset--) { 2436139Sgblack@eecs.umich.edu apicIt++; 2446139Sgblack@eecs.umich.edu assert(apicIt != apics.end()); 2456139Sgblack@eecs.umich.edu } 2466139Sgblack@eecs.umich.edu int selected = *apicIt; 2476139Sgblack@eecs.umich.edu apics.clear(); 2486139Sgblack@eecs.umich.edu apics.push_back(selected); 2496138Sgblack@eecs.umich.edu } 2506138Sgblack@eecs.umich.edu } 2519524SAndreas.Sandberg@ARM.com intMasterPort.sendMessage(apics, message, sys->isTimingMode()); 2525643Sgblack@eecs.umich.edu } 2535643Sgblack@eecs.umich.edu} 2545643Sgblack@eecs.umich.edu 2555827Sgblack@eecs.umich.eduvoid 2565827Sgblack@eecs.umich.eduX86ISA::I82094AA::raiseInterruptPin(int number) 2575827Sgblack@eecs.umich.edu{ 2585827Sgblack@eecs.umich.edu assert(number < TableSize); 2595827Sgblack@eecs.umich.edu if (!pinStates[number]) 2605827Sgblack@eecs.umich.edu signalInterrupt(number); 2615827Sgblack@eecs.umich.edu pinStates[number] = true; 2625827Sgblack@eecs.umich.edu} 2635827Sgblack@eecs.umich.edu 2645827Sgblack@eecs.umich.eduvoid 2655827Sgblack@eecs.umich.eduX86ISA::I82094AA::lowerInterruptPin(int number) 2665827Sgblack@eecs.umich.edu{ 2675827Sgblack@eecs.umich.edu assert(number < TableSize); 2685827Sgblack@eecs.umich.edu pinStates[number] = false; 2695827Sgblack@eecs.umich.edu} 2705827Sgblack@eecs.umich.edu 2716137Sgblack@eecs.umich.eduvoid 27210905Sandreas.sandberg@arm.comX86ISA::I82094AA::serialize(CheckpointOut &cp) const 2737903Shestness@cs.utexas.edu{ 2747903Shestness@cs.utexas.edu uint64_t* redirTableArray = (uint64_t*)redirTable; 2757903Shestness@cs.utexas.edu SERIALIZE_SCALAR(regSel); 2767903Shestness@cs.utexas.edu SERIALIZE_SCALAR(initialApicId); 2777903Shestness@cs.utexas.edu SERIALIZE_SCALAR(id); 2787903Shestness@cs.utexas.edu SERIALIZE_SCALAR(arbId); 2797903Shestness@cs.utexas.edu SERIALIZE_SCALAR(lowestPriorityOffset); 2807903Shestness@cs.utexas.edu SERIALIZE_ARRAY(redirTableArray, TableSize); 2817903Shestness@cs.utexas.edu SERIALIZE_ARRAY(pinStates, TableSize); 2827903Shestness@cs.utexas.edu} 2837903Shestness@cs.utexas.edu 2847903Shestness@cs.utexas.eduvoid 28510905Sandreas.sandberg@arm.comX86ISA::I82094AA::unserialize(CheckpointIn &cp) 2867903Shestness@cs.utexas.edu{ 2877903Shestness@cs.utexas.edu uint64_t redirTableArray[TableSize]; 2887903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(regSel); 2897903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initialApicId); 2907903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(id); 2917903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(arbId); 2927903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(lowestPriorityOffset); 2937903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(redirTableArray, TableSize); 2947903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(pinStates, TableSize); 2957903Shestness@cs.utexas.edu for (int i = 0; i < TableSize; i++) { 2967903Shestness@cs.utexas.edu redirTable[i] = (RedirTableEntry)redirTableArray[i]; 2977903Shestness@cs.utexas.edu } 2987903Shestness@cs.utexas.edu} 2997903Shestness@cs.utexas.edu 3005643Sgblack@eecs.umich.eduX86ISA::I82094AA * 3015643Sgblack@eecs.umich.eduI82094AAParams::create() 3025643Sgblack@eecs.umich.edu{ 3035643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 3045643Sgblack@eecs.umich.edu} 305