cmos.cc revision 5393
17191Sgblack@eecs.umich.edu/* 27191Sgblack@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 37191Sgblack@eecs.umich.edu * All rights reserved. 47191Sgblack@eecs.umich.edu * 57191Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 67191Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 77191Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 87191Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 97191Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 107191Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 117191Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 127191Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 137191Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147191Sgblack@eecs.umich.edu * this software without specific prior written permission. 157191Sgblack@eecs.umich.edu * 167191Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177191Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187191Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197191Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207191Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217191Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227191Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237191Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247191Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257191Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267191Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277191Sgblack@eecs.umich.edu * 287191Sgblack@eecs.umich.edu * Authors: Gabe Black 297191Sgblack@eecs.umich.edu */ 307191Sgblack@eecs.umich.edu 317191Sgblack@eecs.umich.edu#include "dev/x86/south_bridge/cmos.hh" 327191Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 337191Sgblack@eecs.umich.edu 347191Sgblack@eecs.umich.eduTick 357191Sgblack@eecs.umich.eduX86ISA::Cmos::read(PacketPtr pkt) 367191Sgblack@eecs.umich.edu{ 377191Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 387191Sgblack@eecs.umich.edu switch(pkt->getAddr() - addrRange.start) 397191Sgblack@eecs.umich.edu { 407191Sgblack@eecs.umich.edu case 0x0: 417191Sgblack@eecs.umich.edu pkt->set(address); 427191Sgblack@eecs.umich.edu break; 437191Sgblack@eecs.umich.edu case 0x1: 447191Sgblack@eecs.umich.edu pkt->set(readRegister(address)); 457191Sgblack@eecs.umich.edu break; 467191Sgblack@eecs.umich.edu default: 477308Sgblack@eecs.umich.edu panic("Read from undefined CMOS port.\n"); 487191Sgblack@eecs.umich.edu } 497316Sgblack@eecs.umich.edu return latency; 507316Sgblack@eecs.umich.edu} 517316Sgblack@eecs.umich.edu 527316Sgblack@eecs.umich.eduTick 537316Sgblack@eecs.umich.eduX86ISA::Cmos::write(PacketPtr pkt) 547316Sgblack@eecs.umich.edu{ 557191Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 567191Sgblack@eecs.umich.edu switch(pkt->getAddr() - addrRange.start) 577435Sgblack@eecs.umich.edu { 587191Sgblack@eecs.umich.edu case 0x0: 597191Sgblack@eecs.umich.edu address = pkt->get<uint8_t>(); 607435Sgblack@eecs.umich.edu break; 617191Sgblack@eecs.umich.edu case 0x1: 627191Sgblack@eecs.umich.edu writeRegister(address, pkt->get<uint8_t>()); 637248Sgblack@eecs.umich.edu break; 647191Sgblack@eecs.umich.edu default: 657192Sgblack@eecs.umich.edu panic("Write to undefined CMOS port.\n"); 667192Sgblack@eecs.umich.edu } 677192Sgblack@eecs.umich.edu return latency; 687192Sgblack@eecs.umich.edu} 697192Sgblack@eecs.umich.edu 707192Sgblack@eecs.umich.eduuint8_t 717192Sgblack@eecs.umich.eduX86ISA::Cmos::readRegister(uint8_t reg) 727192Sgblack@eecs.umich.edu{ 737192Sgblack@eecs.umich.edu assert(reg < numRegs); 747191Sgblack@eecs.umich.edu if (reg <= 0xD) { 757191Sgblack@eecs.umich.edu return rtc.readData(reg); 767191Sgblack@eecs.umich.edu } else { 777192Sgblack@eecs.umich.edu warn("Reading non-volitile CMOS address %x as %x.\n", reg, regs[reg]); 787192Sgblack@eecs.umich.edu } 797192Sgblack@eecs.umich.edu return regs[reg]; 807192Sgblack@eecs.umich.edu} 817192Sgblack@eecs.umich.edu 827192Sgblack@eecs.umich.eduvoid 837192Sgblack@eecs.umich.eduX86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val) 847192Sgblack@eecs.umich.edu{ 857192Sgblack@eecs.umich.edu assert(reg < numRegs); 867192Sgblack@eecs.umich.edu if (reg <= 0xD) { 877192Sgblack@eecs.umich.edu rtc.writeData(reg, val); 887192Sgblack@eecs.umich.edu return; 897192Sgblack@eecs.umich.edu } else { 907192Sgblack@eecs.umich.edu warn("Writing non-volitile CMOS address %x with %x.\n", reg, val); 917192Sgblack@eecs.umich.edu } 927192Sgblack@eecs.umich.edu regs[reg] = val; 937192Sgblack@eecs.umich.edu} 947192Sgblack@eecs.umich.edu