cmos.cc revision 5634
15390SN/A/* 25390SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Gabe Black 295390SN/A */ 305390SN/A 315629Sgblack@eecs.umich.edu#include "dev/x86/cmos.hh" 325634Sgblack@eecs.umich.edu#include "dev/x86/intdev.hh" 335390SN/A#include "mem/packet_access.hh" 345390SN/A 355632Sgblack@eecs.umich.eduvoid 365632Sgblack@eecs.umich.eduX86ISA::Cmos::X86RTC::handleEvent() 375632Sgblack@eecs.umich.edu{ 385634Sgblack@eecs.umich.edu assert(intPin); 395634Sgblack@eecs.umich.edu intPin->signalInterrupt(); 405632Sgblack@eecs.umich.edu} 415632Sgblack@eecs.umich.edu 425390SN/ATick 435390SN/AX86ISA::Cmos::read(PacketPtr pkt) 445390SN/A{ 455390SN/A assert(pkt->getSize() == 1); 465629Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 475390SN/A { 485390SN/A case 0x0: 495390SN/A pkt->set(address); 505390SN/A break; 515390SN/A case 0x1: 525390SN/A pkt->set(readRegister(address)); 535390SN/A break; 545390SN/A default: 555390SN/A panic("Read from undefined CMOS port.\n"); 565390SN/A } 575390SN/A return latency; 585390SN/A} 595390SN/A 605390SN/ATick 615390SN/AX86ISA::Cmos::write(PacketPtr pkt) 625390SN/A{ 635390SN/A assert(pkt->getSize() == 1); 645629Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 655390SN/A { 665390SN/A case 0x0: 675390SN/A address = pkt->get<uint8_t>(); 685390SN/A break; 695390SN/A case 0x1: 705390SN/A writeRegister(address, pkt->get<uint8_t>()); 715390SN/A break; 725390SN/A default: 735390SN/A panic("Write to undefined CMOS port.\n"); 745390SN/A } 755390SN/A return latency; 765390SN/A} 775390SN/A 785390SN/Auint8_t 795390SN/AX86ISA::Cmos::readRegister(uint8_t reg) 805390SN/A{ 815390SN/A assert(reg < numRegs); 825629Sgblack@eecs.umich.edu uint8_t val; 835393SN/A if (reg <= 0xD) { 845629Sgblack@eecs.umich.edu val = rtc.readData(reg); 855629Sgblack@eecs.umich.edu DPRINTF(CMOS, 865629Sgblack@eecs.umich.edu "Reading CMOS RTC reg %x as %x.\n", reg, val); 875393SN/A } else { 885629Sgblack@eecs.umich.edu val = regs[reg]; 895629Sgblack@eecs.umich.edu DPRINTF(CMOS, 905629Sgblack@eecs.umich.edu "Reading non-volitile CMOS address %x as %x.\n", reg, val); 915390SN/A } 925629Sgblack@eecs.umich.edu return val; 935390SN/A} 945390SN/A 955390SN/Avoid 965390SN/AX86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val) 975390SN/A{ 985390SN/A assert(reg < numRegs); 995393SN/A if (reg <= 0xD) { 1005629Sgblack@eecs.umich.edu DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n", 1015629Sgblack@eecs.umich.edu reg, val); 1025393SN/A rtc.writeData(reg, val); 1035393SN/A } else { 1045629Sgblack@eecs.umich.edu DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n", 1055629Sgblack@eecs.umich.edu reg, val); 1065629Sgblack@eecs.umich.edu regs[reg] = val; 1075390SN/A } 1085390SN/A} 1095629Sgblack@eecs.umich.edu 1105629Sgblack@eecs.umich.eduX86ISA::Cmos * 1115629Sgblack@eecs.umich.eduCmosParams::create() 1125629Sgblack@eecs.umich.edu{ 1135629Sgblack@eecs.umich.edu return new X86ISA::Cmos(this); 1145629Sgblack@eecs.umich.edu} 115