Pc.py revision 9983
1# Copyright (c) 2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Gabe Black 28 29from m5.params import * 30from m5.proxy import * 31 32from Device import IsaFake 33from Pci import PciConfigAll 34from Platform import Platform 35from SouthBridge import SouthBridge 36from Terminal import Terminal 37from Uart import Uart8250 38 39def x86IOAddress(port): 40 IO_address_space_base = 0x8000000000000000 41 return IO_address_space_base + port; 42 43class Pc(Platform): 44 type = 'Pc' 45 cxx_header = "dev/x86/pc.hh" 46 system = Param.System(Parent.any, "system") 47 48 pciconfig = PciConfigAll() 49 50 south_bridge = SouthBridge() 51 52 # "Non-existant" port used for timing purposes by the linux kernel 53 i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) 54 55 # Ports behind the pci config and data regsiters. These don't do anything, 56 # but the linux kernel fiddles with them anway. 57 behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) 58 59 # Serial port and terminal 60 com_1 = Uart8250() 61 com_1.pio_addr = x86IOAddress(0x3f8) 62 com_1.terminal = Terminal() 63 64 # Devices to catch access to non-existant serial ports. 65 fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8) 66 fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8) 67 fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8) 68 69 # A device to catch accesses to the non-existant floppy controller. 70 fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2) 71 72 def attachIO(self, bus, dma_ports = []): 73 self.south_bridge.attachIO(bus, dma_ports) 74 self.i_dont_exist.pio = bus.master 75 self.behind_pci.pio = bus.master 76 self.com_1.pio = bus.master 77 self.fake_com_2.pio = bus.master 78 self.fake_com_3.pio = bus.master 79 self.fake_com_4.pio = bus.master 80 self.fake_floppy.pio = bus.master 81 self.pciconfig.pio = bus.default 82 bus.use_default_range = True 83