Pc.py revision 5390 
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
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7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31from Uart import Uart8250
32from Device import IsaFake
33from SouthBridge import SouthBridge
34from Platform import Platform
35from Pci import PciConfigAll
36from SimConsole import SimConsole
37
38def x86IOAddress(port):
39    IO_address_space_base = 0x8000000000000000
40    return IO_address_space_base + port;
41
42class PC(Platform):
43    type = 'PC'
44    system = Param.System(Parent.any, "system")
45
46    pciconfig = PciConfigAll()
47
48    south_bridge = SouthBridge()
49
50    # "Non-existant" port used for timing purposes by the linux kernel
51    i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
52
53    # Serial port and console
54    console = SimConsole()
55    com_1 = Uart8250()
56    com_1.pio_addr = x86IOAddress(0x3f8)
57    com_1.sim_console = console
58
59    def attachIO(self, bus):
60        self.south_bridge.pio = bus.port
61        self.i_dont_exist.pio = bus.port
62        self.com_1.pio = bus.port
63        self.pciconfig.pio = bus.default
64        bus.responder_set = True
65        bus.responder = self.pciconfig
66