Pc.py revision 11244
15389SN/A# Copyright (c) 2008 The Regents of The University of Michigan 25389SN/A# All rights reserved. 35389SN/A# 45389SN/A# Redistribution and use in source and binary forms, with or without 55389SN/A# modification, are permitted provided that the following conditions are 65389SN/A# met: redistributions of source code must retain the above copyright 75389SN/A# notice, this list of conditions and the following disclaimer; 85389SN/A# redistributions in binary form must reproduce the above copyright 95389SN/A# notice, this list of conditions and the following disclaimer in the 105389SN/A# documentation and/or other materials provided with the distribution; 115389SN/A# neither the name of the copyright holders nor the names of its 125389SN/A# contributors may be used to endorse or promote products derived from 135389SN/A# this software without specific prior written permission. 145389SN/A# 155389SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165389SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175389SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185389SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195389SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205389SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215389SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225389SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235389SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245389SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255389SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265389SN/A# 275389SN/A# Authors: Gabe Black 285389SN/A 295389SN/Afrom m5.params import * 305389SN/Afrom m5.proxy import * 315478SN/A 325478SN/Afrom Device import IsaFake 335478SN/Afrom Platform import Platform 345478SN/Afrom SouthBridge import SouthBridge 355478SN/Afrom Terminal import Terminal 365389SN/Afrom Uart import Uart8250 3711244Sandreas.sandberg@arm.comfrom PciHost import GenericPciHost 385389SN/A 395389SN/Adef x86IOAddress(port): 405389SN/A IO_address_space_base = 0x8000000000000000 415389SN/A return IO_address_space_base + port; 425389SN/A 4311244Sandreas.sandberg@arm.comclass PcPciHost(GenericPciHost): 4411244Sandreas.sandberg@arm.com conf_base = 0xC000000000000000 4511244Sandreas.sandberg@arm.com conf_size = "16MB" 4611244Sandreas.sandberg@arm.com 4711244Sandreas.sandberg@arm.com pci_pio_base = 0x8000000000000000 4811244Sandreas.sandberg@arm.com 495638Sgblack@eecs.umich.educlass Pc(Platform): 505638Sgblack@eecs.umich.edu type = 'Pc' 519338SAndreas.Sandberg@arm.com cxx_header = "dev/x86/pc.hh" 525389SN/A system = Param.System(Parent.any, "system") 535389SN/A 545390SN/A south_bridge = SouthBridge() 5511244Sandreas.sandberg@arm.com pci_host = PcPciHost() 565390SN/A 5710548Sgabeblack@google.com # "Non-existant" ports used for timing purposes by the linux kernel 5810548Sgabeblack@google.com i_dont_exist1 = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) 5910548Sgabeblack@google.com i_dont_exist2 = IsaFake(pio_addr=x86IOAddress(0xed), pio_size=1) 605390SN/A 615447SN/A # Ports behind the pci config and data regsiters. These don't do anything, 625447SN/A # but the linux kernel fiddles with them anway. 635447SN/A behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) 645447SN/A 655478SN/A # Serial port and terminal 665389SN/A com_1 = Uart8250() 675389SN/A com_1.pio_addr = x86IOAddress(0x3f8) 689983Sstever@gmail.com com_1.terminal = Terminal() 695389SN/A 705816Sgblack@eecs.umich.edu # Devices to catch access to non-existant serial ports. 715816Sgblack@eecs.umich.edu fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8) 725816Sgblack@eecs.umich.edu fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8) 735816Sgblack@eecs.umich.edu fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8) 745816Sgblack@eecs.umich.edu 755817Sgblack@eecs.umich.edu # A device to catch accesses to the non-existant floppy controller. 765833Sgblack@eecs.umich.edu fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2) 775817Sgblack@eecs.umich.edu 788929Snilay@cs.wisc.edu def attachIO(self, bus, dma_ports = []): 798929Snilay@cs.wisc.edu self.south_bridge.attachIO(bus, dma_ports) 8010548Sgabeblack@google.com self.i_dont_exist1.pio = bus.master 8110548Sgabeblack@google.com self.i_dont_exist2.pio = bus.master 828839Sandreas.hansson@arm.com self.behind_pci.pio = bus.master 838839Sandreas.hansson@arm.com self.com_1.pio = bus.master 848839Sandreas.hansson@arm.com self.fake_com_2.pio = bus.master 858839Sandreas.hansson@arm.com self.fake_com_3.pio = bus.master 868839Sandreas.hansson@arm.com self.fake_com_4.pio = bus.master 878839Sandreas.hansson@arm.com self.fake_floppy.pio = bus.master 8811244Sandreas.sandberg@arm.com self.pci_host.pio = bus.default 89