1/*
2 * Copyright (c) 2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Andrew Schultz
41 */
42
43/** @file
44 * Device model for an IDE disk
45 */
46
47#ifndef __DEV_STORAGE_IDE_DISK_HH__
48#define __DEV_STORAGE_IDE_DISK_HH__
49
50#include "base/statistics.hh"
51#include "dev/io_device.hh"
52#include "dev/storage/disk_image.hh"
53#include "dev/storage/ide_atareg.h"
54#include "dev/storage/ide_ctrl.hh"
55#include "dev/storage/ide_wdcreg.h"
56#include "params/IdeDisk.hh"
57#include "sim/eventq.hh"
58
59class ChunkGenerator;
60
61#define DMA_BACKOFF_PERIOD      200
62
63#define MAX_DMA_SIZE            0x20000  // 128K
64#define MAX_SINGLE_DMA_SIZE     0x10000
65#define MAX_MULTSECT            (128)
66
67#define PRD_BASE_MASK  0xfffffffe
68#define PRD_COUNT_MASK 0xfffe
69#define PRD_EOT_MASK   0x8000
70
71typedef struct PrdEntry {
72    uint32_t baseAddr;
73    uint16_t byteCount;
74    uint16_t endOfTable;
75} PrdEntry_t;
76
77class PrdTableEntry {
78  public:
79    PrdEntry_t entry;
80
81    uint32_t getBaseAddr()
82    {
83        return (entry.baseAddr & PRD_BASE_MASK);
84    }
85
86    uint32_t getByteCount()
87    {
88        return ((entry.byteCount == 0) ? MAX_SINGLE_DMA_SIZE :
89                (entry.byteCount & PRD_COUNT_MASK));
90    }
91
92    uint16_t getEOT()
93    {
94        return (entry.endOfTable & PRD_EOT_MASK);
95    }
96};
97
98#define DATA_OFFSET     (0)
99#define ERROR_OFFSET    (1)
100#define FEATURES_OFFSET (1)
101#define NSECTOR_OFFSET  (2)
102#define SECTOR_OFFSET   (3)
103#define LCYL_OFFSET     (4)
104#define HCYL_OFFSET     (5)
105#define SELECT_OFFSET   (6)
106#define DRIVE_OFFSET    (6)
107#define STATUS_OFFSET   (7)
108#define COMMAND_OFFSET  (7)
109
110#define CONTROL_OFFSET  (2)
111#define ALTSTAT_OFFSET  (2)
112
113#define SELECT_DEV_BIT  0x10
114#define CONTROL_RST_BIT 0x04
115#define CONTROL_IEN_BIT 0x02
116#define STATUS_BSY_BIT  0x80
117#define STATUS_DRDY_BIT 0x40
118#define STATUS_DRQ_BIT  0x08
119#define STATUS_SEEK_BIT 0x10
120#define STATUS_DF_BIT   0x20
121#define DRIVE_LBA_BIT   0x40
122
123#define DEV0 (0)
124#define DEV1 (1)
125
126typedef struct CommandReg {
127    uint16_t data;
128    uint8_t error;
129    uint8_t sec_count;
130    uint8_t sec_num;
131    uint8_t cyl_low;
132    uint8_t cyl_high;
133    union {
134        uint8_t drive;
135        uint8_t head;
136    };
137    uint8_t command;
138} CommandReg_t;
139
140typedef enum Events {
141    None = 0,
142    Transfer,
143    ReadWait,
144    WriteWait,
145    PrdRead,
146    DmaRead,
147    DmaWrite
148} Events_t;
149
150typedef enum DevAction {
151    ACT_NONE = 0,
152    ACT_CMD_WRITE,
153    ACT_CMD_COMPLETE,
154    ACT_CMD_ERROR,
155    ACT_SELECT_WRITE,
156    ACT_STAT_READ,
157    ACT_DATA_READY,
158    ACT_DATA_READ_BYTE,
159    ACT_DATA_READ_SHORT,
160    ACT_DATA_WRITE_BYTE,
161    ACT_DATA_WRITE_SHORT,
162    ACT_DMA_READY,
163    ACT_DMA_DONE,
164    ACT_SRST_SET,
165    ACT_SRST_CLEAR
166} DevAction_t;
167
168typedef enum DevState {
169    // Device idle
170    Device_Idle_S = 0,
171    Device_Idle_SI,
172    Device_Idle_NS,
173
174    // Software reset
175    Device_Srst,
176
177    // Non-data commands
178    Command_Execution,
179
180    // PIO data-in (data to host)
181    Prepare_Data_In,
182    Data_Ready_INTRQ_In,
183    Transfer_Data_In,
184
185    // PIO data-out (data from host)
186    Prepare_Data_Out,
187    Data_Ready_INTRQ_Out,
188    Transfer_Data_Out,
189
190    // DMA protocol
191    Prepare_Data_Dma,
192    Transfer_Data_Dma,
193    Device_Dma_Abort
194} DevState_t;
195
196typedef enum DmaState {
197    Dma_Idle = 0,
198    Dma_Start,
199    Dma_Transfer
200} DmaState_t;
201
202class IdeController;
203
204/**
205 * IDE Disk device model
206 */
207class IdeDisk : public SimObject
208{
209  protected:
210    /** The IDE controller for this disk. */
211    IdeController *ctrl;
212    /** The image that contains the data of this disk. */
213    DiskImage *image;
214
215  protected:
216    /** The disk delay in microseconds. */
217    int diskDelay;
218
219  private:
220    /** Drive identification structure for this disk */
221    struct ataparams driveID;
222    /** Data buffer for transfers */
223    uint8_t *dataBuffer;
224    /** Number of bytes in command data transfer */
225    uint32_t cmdBytes;
226    /** Number of bytes left in command data transfer */
227    uint32_t cmdBytesLeft;
228    /** Number of bytes left in DRQ block */
229    uint32_t drqBytesLeft;
230    /** Current sector in access */
231    uint32_t curSector;
232    /** Command block registers */
233    CommandReg_t cmdReg;
234    /** Status register */
235    uint8_t status;
236    /** Interrupt enable bit */
237    bool nIENBit;
238    /** Device state */
239    DevState_t devState;
240    /** Dma state */
241    DmaState_t dmaState;
242    /** Dma transaction is a read */
243    bool dmaRead;
244    /** PRD table base address */
245    uint32_t curPrdAddr;
246    /** PRD entry */
247    PrdTableEntry curPrd;
248    /** Device ID (master=0/slave=1) */
249    int devID;
250    /** Interrupt pending */
251    bool intrPending;
252    /** DMA Aborted */
253    bool dmaAborted;
254
255    Stats::Scalar dmaReadFullPages;
256    Stats::Scalar dmaReadBytes;
257    Stats::Scalar dmaReadTxs;
258    Stats::Scalar dmaWriteFullPages;
259    Stats::Scalar dmaWriteBytes;
260    Stats::Scalar dmaWriteTxs;
261
262  public:
263    typedef IdeDiskParams Params;
264    IdeDisk(const Params *p);
265
266    /**
267     * Delete the data buffer.
268     */
269    ~IdeDisk();
270
271    /**
272     * Reset the device state
273     */
274    void reset(int id);
275
276    /**
277     * Register Statistics
278     */
279    void regStats() override;
280
281    /**
282     * Set the controller for this device
283     * @param c The IDE controller
284     */
285    void setController(IdeController *c) {
286        if (ctrl) panic("Cannot change the controller once set!\n");
287        ctrl = c;
288    }
289
290    // Device register read/write
291    void readCommand(const Addr offset, int size, uint8_t *data);
292    void readControl(const Addr offset, int size, uint8_t *data);
293    void writeCommand(const Addr offset, int size, const uint8_t *data);
294    void writeControl(const Addr offset, int size, const uint8_t *data);
295
296    // Start/abort functions
297    void startDma(const uint32_t &prdTableBase);
298    void abortDma();
299
300  private:
301    void startCommand();
302
303    // Interrupt management
304    void intrPost();
305    void intrClear();
306
307    // DMA stuff
308    void doDmaTransfer();
309    EventFunctionWrapper dmaTransferEvent;
310
311    void doDmaDataRead();
312
313    void doDmaRead();
314    ChunkGenerator *dmaReadCG;
315    EventFunctionWrapper dmaReadWaitEvent;
316
317    void doDmaDataWrite();
318
319    void doDmaWrite();
320    ChunkGenerator *dmaWriteCG;
321    EventFunctionWrapper dmaWriteWaitEvent;
322
323    void dmaPrdReadDone();
324    EventFunctionWrapper dmaPrdReadEvent;
325
326    void dmaReadDone();
327    EventFunctionWrapper dmaReadEvent;
328
329    void dmaWriteDone();
330    EventFunctionWrapper dmaWriteEvent;
331
332    // Disk image read/write
333    void readDisk(uint32_t sector, uint8_t *data);
334    void writeDisk(uint32_t sector, uint8_t *data);
335
336    // State machine management
337    void updateState(DevAction_t action);
338
339    // Utility functions
340    bool isBSYSet() { return (status & STATUS_BSY_BIT); }
341    bool isIENSet() { return nIENBit; }
342    bool isDEVSelect();
343
344    void setComplete()
345    {
346        // clear out the status byte
347        status = 0;
348        // set the DRDY bit
349        status |= STATUS_DRDY_BIT;
350        // set the SEEK bit
351        status |= STATUS_SEEK_BIT;
352    }
353
354    uint32_t getLBABase()
355    {
356        return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
357                       (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
358    }
359
360    inline Addr pciToDma(Addr pciAddr);
361
362    void serialize(CheckpointOut &cp) const override;
363    void unserialize(CheckpointIn &cp) override;
364};
365
366
367#endif // __DEV_STORAGE_IDE_DISK_HH__
368