iob.hh revision 11347
114039Sstacze01@arm.com/*
214039Sstacze01@arm.com * Copyright (c) 2006 The Regents of The University of Michigan
314039Sstacze01@arm.com * All rights reserved.
414039Sstacze01@arm.com *
514039Sstacze01@arm.com * Redistribution and use in source and binary forms, with or without
614039Sstacze01@arm.com * modification, are permitted provided that the following conditions are
714039Sstacze01@arm.com * met: redistributions of source code must retain the above copyright
814039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer;
914039Sstacze01@arm.com * redistributions in binary form must reproduce the above copyright
1014039Sstacze01@arm.com * notice, this list of conditions and the following disclaimer in the
1114039Sstacze01@arm.com * documentation and/or other materials provided with the distribution;
1214039Sstacze01@arm.com * neither the name of the copyright holders nor the names of its
1314039Sstacze01@arm.com * contributors may be used to endorse or promote products derived from
1414039Sstacze01@arm.com * this software without specific prior written permission.
1514039Sstacze01@arm.com *
1614039Sstacze01@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1714039Sstacze01@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1814039Sstacze01@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1914039Sstacze01@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2014039Sstacze01@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2114039Sstacze01@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2214039Sstacze01@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2314039Sstacze01@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2414039Sstacze01@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2514039Sstacze01@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2614039Sstacze01@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2714039Sstacze01@arm.com *
2814039Sstacze01@arm.com * Authors: Ali Saidi
2914039Sstacze01@arm.com */
3014039Sstacze01@arm.com
3114039Sstacze01@arm.com/** @file
3214039Sstacze01@arm.com * This device implements the niagara I/O Bridge chip. The device manages
3314039Sstacze01@arm.com * internal (ipi) and external (serial, pci via jbus).
3414039Sstacze01@arm.com */
3514039Sstacze01@arm.com
3614039Sstacze01@arm.com#ifndef __DEV_SPARC_IOB_HH__
3714039Sstacze01@arm.com#define __DEV_SPARC_IOB_HH__
3814039Sstacze01@arm.com
3914039Sstacze01@arm.com#include "dev/io_device.hh"
4014039Sstacze01@arm.com#include "params/Iob.hh"
4114039Sstacze01@arm.com
4214039Sstacze01@arm.comclass IntrControl;
4314039Sstacze01@arm.com
4414039Sstacze01@arm.comconst int  MaxNiagaraProcs = 32;
4514039Sstacze01@arm.com// IOB Managment Addresses
4614039Sstacze01@arm.comconst Addr IntManAddr       = 0x0000;
4714039Sstacze01@arm.comconst Addr IntManSize       = 0x0020;
4814039Sstacze01@arm.comconst Addr IntCtlAddr       = 0x0400;
4914039Sstacze01@arm.comconst Addr IntCtlSize       = 0x0020;
5014039Sstacze01@arm.comconst Addr JIntVecAddr      = 0x0A00;
5114039Sstacze01@arm.comconst Addr IntVecDisAddr    = 0x0800;
5214039Sstacze01@arm.comconst Addr IntVecDisSize    = 0x0100;
5314039Sstacze01@arm.com
5414039Sstacze01@arm.com
5514039Sstacze01@arm.com// IOB Control Addresses
5614039Sstacze01@arm.comconst Addr JIntData0Addr   = 0x0400;
5714039Sstacze01@arm.comconst Addr JIntData1Addr   = 0x0500;
5814039Sstacze01@arm.comconst Addr JIntDataA0Addr  = 0x0600;
5914064Sadrian.herrera@arm.comconst Addr JIntDataA1Addr  = 0x0700;
6014064Sadrian.herrera@arm.comconst Addr JIntBusyAddr    = 0x0900;
6114064Sadrian.herrera@arm.comconst Addr JIntBusySize    = 0x0100;
6214039Sstacze01@arm.comconst Addr JIntABusyAddr   = 0x0B00;
6314039Sstacze01@arm.com
6414039Sstacze01@arm.com
6514039Sstacze01@arm.com// IOB Masks
6614039Sstacze01@arm.comconst uint64_t IntManMask   = 0x01F3F;
6714039Sstacze01@arm.comconst uint64_t IntCtlMask   = 0x00006;
6814039Sstacze01@arm.comconst uint64_t JIntVecMask  = 0x0003F;
6914039Sstacze01@arm.comconst uint64_t IntVecDis    = 0x31F3F;
7014039Sstacze01@arm.comconst uint64_t JIntBusyMask = 0x0003F;
7114039Sstacze01@arm.com
7214039Sstacze01@arm.com
7314039Sstacze01@arm.comclass Iob : public PioDevice
7414039Sstacze01@arm.com{
7514039Sstacze01@arm.com  private:
7614039Sstacze01@arm.com    IntrControl *ic;
7714039Sstacze01@arm.com    Addr iobManAddr;
7814039Sstacze01@arm.com    Addr iobManSize;
7914039Sstacze01@arm.com    Addr iobJBusAddr;
8014039Sstacze01@arm.com    Addr iobJBusSize;
8114039Sstacze01@arm.com    Tick pioDelay;
8214039Sstacze01@arm.com
8314039Sstacze01@arm.com    enum DeviceId {
8414039Sstacze01@arm.com        Interal = 0,
8514039Sstacze01@arm.com        Error = 1,
8614039Sstacze01@arm.com        SSI = 2,
8714039Sstacze01@arm.com        Reserved = 3,
8814039Sstacze01@arm.com        NumDeviceIds
8914039Sstacze01@arm.com    };
9014039Sstacze01@arm.com
9114039Sstacze01@arm.com    struct IntMan {
9214039Sstacze01@arm.com        int cpu;
9314039Sstacze01@arm.com        int vector;
9414039Sstacze01@arm.com    };
9514039Sstacze01@arm.com
9614039Sstacze01@arm.com    struct IntCtl {
9714039Sstacze01@arm.com        bool mask;
9814039Sstacze01@arm.com        bool pend;
9914039Sstacze01@arm.com    };
10014039Sstacze01@arm.com
10114039Sstacze01@arm.com    struct IntBusy {
10214039Sstacze01@arm.com        bool busy;
10314039Sstacze01@arm.com        int source;
10414039Sstacze01@arm.com    };
10514039Sstacze01@arm.com
10614039Sstacze01@arm.com    enum Type {
10714039Sstacze01@arm.com        Interrupt,
10814039Sstacze01@arm.com        Reset,
10914039Sstacze01@arm.com        Idle,
11014039Sstacze01@arm.com        Resume
11114039Sstacze01@arm.com    };
11214039Sstacze01@arm.com
11314039Sstacze01@arm.com    IntMan intMan[NumDeviceIds];
11414039Sstacze01@arm.com    IntCtl intCtl[NumDeviceIds];
11514039Sstacze01@arm.com    uint64_t jIntVec;
11614039Sstacze01@arm.com    uint64_t jBusData0[MaxNiagaraProcs];
11714039Sstacze01@arm.com    uint64_t jBusData1[MaxNiagaraProcs];
11814039Sstacze01@arm.com    IntBusy jIntBusy[MaxNiagaraProcs];
11914039Sstacze01@arm.com
12014039Sstacze01@arm.com    void writeIob(PacketPtr pkt);
12114039Sstacze01@arm.com    void writeJBus(PacketPtr pkt);
12214039Sstacze01@arm.com    void readIob(PacketPtr pkt);
12314039Sstacze01@arm.com    void readJBus(PacketPtr pkt);
12414039Sstacze01@arm.com
12514039Sstacze01@arm.com  public:
12614039Sstacze01@arm.com    typedef IobParams Params;
12714039Sstacze01@arm.com    Iob(const Params *p);
12814039Sstacze01@arm.com
12914039Sstacze01@arm.com    const Params *
13014064Sadrian.herrera@arm.com    params() const
13114064Sadrian.herrera@arm.com    {
13214064Sadrian.herrera@arm.com        return dynamic_cast<const Params *>(_params);
13314064Sadrian.herrera@arm.com    }
13414064Sadrian.herrera@arm.com
13514064Sadrian.herrera@arm.com    Tick read(PacketPtr pkt) override;
13614064Sadrian.herrera@arm.com    Tick write(PacketPtr pkt) override;
13714064Sadrian.herrera@arm.com    void generateIpi(Type type, int cpu_id, int vector);
13814039Sstacze01@arm.com    void receiveDeviceInterrupt(DeviceId devid);
13914039Sstacze01@arm.com    bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
14014039Sstacze01@arm.com                              uint64_t d1);
14114039Sstacze01@arm.com
14214039Sstacze01@arm.com    AddrRangeList getAddrRanges() const override;
143
144    void serialize(CheckpointOut &cp) const override;
145    void unserialize(CheckpointIn &cp) override;
146};
147
148#endif //__DEV_SPARC_IOB_HH__
149
150