iob.hh revision 11347
12221SN/A/*
22221SN/A * Copyright (c) 2006 The Regents of The University of Michigan
32221SN/A * All rights reserved.
42221SN/A *
52221SN/A * Redistribution and use in source and binary forms, with or without
62221SN/A * modification, are permitted provided that the following conditions are
72221SN/A * met: redistributions of source code must retain the above copyright
82221SN/A * notice, this list of conditions and the following disclaimer;
92221SN/A * redistributions in binary form must reproduce the above copyright
102221SN/A * notice, this list of conditions and the following disclaimer in the
112221SN/A * documentation and/or other materials provided with the distribution;
122221SN/A * neither the name of the copyright holders nor the names of its
132221SN/A * contributors may be used to endorse or promote products derived from
142221SN/A * this software without specific prior written permission.
152221SN/A *
162221SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172221SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182221SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192221SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202221SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212221SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222221SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232221SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242221SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252221SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262221SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Ali Saidi
292665Ssaidi@eecs.umich.edu */
302221SN/A
312221SN/A/** @file
323890Ssaidi@eecs.umich.edu * This device implements the niagara I/O Bridge chip. The device manages
333890Ssaidi@eecs.umich.edu * internal (ipi) and external (serial, pci via jbus).
342221SN/A */
354997Sgblack@eecs.umich.edu
367678Sgblack@eecs.umich.edu#ifndef __DEV_SPARC_IOB_HH__
372221SN/A#define __DEV_SPARC_IOB_HH__
382221SN/A
392221SN/A#include "dev/io_device.hh"
402221SN/A#include "params/Iob.hh"
412223SN/A
422221SN/Aclass IntrControl;
432221SN/A
443415Sgblack@eecs.umich.educonst int  MaxNiagaraProcs = 32;
453415Sgblack@eecs.umich.edu// IOB Managment Addresses
462221SN/Aconst Addr IntManAddr       = 0x0000;
474997Sgblack@eecs.umich.educonst Addr IntManSize       = 0x0020;
484997Sgblack@eecs.umich.educonst Addr IntCtlAddr       = 0x0400;
493573Sgblack@eecs.umich.educonst Addr IntCtlSize       = 0x0020;
502221SN/Aconst Addr JIntVecAddr      = 0x0A00;
512221SN/Aconst Addr IntVecDisAddr    = 0x0800;
523576Sgblack@eecs.umich.educonst Addr IntVecDisSize    = 0x0100;
533576Sgblack@eecs.umich.edu
543576Sgblack@eecs.umich.edu
553576Sgblack@eecs.umich.edu// IOB Control Addresses
563576Sgblack@eecs.umich.educonst Addr JIntData0Addr   = 0x0400;
573576Sgblack@eecs.umich.educonst Addr JIntData1Addr   = 0x0500;
583576Sgblack@eecs.umich.educonst Addr JIntDataA0Addr  = 0x0600;
593576Sgblack@eecs.umich.educonst Addr JIntDataA1Addr  = 0x0700;
603576Sgblack@eecs.umich.educonst Addr JIntBusyAddr    = 0x0900;
613573Sgblack@eecs.umich.educonst Addr JIntBusySize    = 0x0100;
623573Sgblack@eecs.umich.educonst Addr JIntABusyAddr   = 0x0B00;
633573Sgblack@eecs.umich.edu
643573Sgblack@eecs.umich.edu
653573Sgblack@eecs.umich.edu// IOB Masks
663576Sgblack@eecs.umich.educonst uint64_t IntManMask   = 0x01F3F;
673573Sgblack@eecs.umich.educonst uint64_t IntCtlMask   = 0x00006;
683573Sgblack@eecs.umich.educonst uint64_t JIntVecMask  = 0x0003F;
692221SN/Aconst uint64_t IntVecDis    = 0x31F3F;
707678Sgblack@eecs.umich.educonst uint64_t JIntBusyMask = 0x0003F;
717678Sgblack@eecs.umich.edu
722221SN/A
732223SN/Aclass Iob : public PioDevice
742223SN/A{
752223SN/A  private:
763576Sgblack@eecs.umich.edu    IntrControl *ic;
772221SN/A    Addr iobManAddr;
782221SN/A    Addr iobManSize;
793573Sgblack@eecs.umich.edu    Addr iobJBusAddr;
803573Sgblack@eecs.umich.edu    Addr iobJBusSize;
812221SN/A    Tick pioDelay;
823573Sgblack@eecs.umich.edu
833573Sgblack@eecs.umich.edu    enum DeviceId {
842221SN/A        Interal = 0,
854695Sgblack@eecs.umich.edu        Error = 1,
863573Sgblack@eecs.umich.edu        SSI = 2,
873573Sgblack@eecs.umich.edu        Reserved = 3,
883573Sgblack@eecs.umich.edu        NumDeviceIds
893576Sgblack@eecs.umich.edu    };
903576Sgblack@eecs.umich.edu
913576Sgblack@eecs.umich.edu    struct IntMan {
923576Sgblack@eecs.umich.edu        int cpu;
933573Sgblack@eecs.umich.edu        int vector;
943573Sgblack@eecs.umich.edu    };
953576Sgblack@eecs.umich.edu
963576Sgblack@eecs.umich.edu    struct IntCtl {
977678Sgblack@eecs.umich.edu        bool mask;
987678Sgblack@eecs.umich.edu        bool pend;
997678Sgblack@eecs.umich.edu    };
1007678Sgblack@eecs.umich.edu
1013576Sgblack@eecs.umich.edu    struct IntBusy {
1023576Sgblack@eecs.umich.edu        bool busy;
1033576Sgblack@eecs.umich.edu        int source;
1043576Sgblack@eecs.umich.edu    };
1053576Sgblack@eecs.umich.edu
1063576Sgblack@eecs.umich.edu    enum Type {
1073576Sgblack@eecs.umich.edu        Interrupt,
1083576Sgblack@eecs.umich.edu        Reset,
1093576Sgblack@eecs.umich.edu        Idle,
1103576Sgblack@eecs.umich.edu        Resume
1113576Sgblack@eecs.umich.edu    };
1123576Sgblack@eecs.umich.edu
1133576Sgblack@eecs.umich.edu    IntMan intMan[NumDeviceIds];
1143576Sgblack@eecs.umich.edu    IntCtl intCtl[NumDeviceIds];
1153576Sgblack@eecs.umich.edu    uint64_t jIntVec;
1163576Sgblack@eecs.umich.edu    uint64_t jBusData0[MaxNiagaraProcs];
1173576Sgblack@eecs.umich.edu    uint64_t jBusData1[MaxNiagaraProcs];
1183576Sgblack@eecs.umich.edu    IntBusy jIntBusy[MaxNiagaraProcs];
1193576Sgblack@eecs.umich.edu
1203576Sgblack@eecs.umich.edu    void writeIob(PacketPtr pkt);
1213576Sgblack@eecs.umich.edu    void writeJBus(PacketPtr pkt);
1223576Sgblack@eecs.umich.edu    void readIob(PacketPtr pkt);
1233576Sgblack@eecs.umich.edu    void readJBus(PacketPtr pkt);
1243576Sgblack@eecs.umich.edu
1253576Sgblack@eecs.umich.edu  public:
1263576Sgblack@eecs.umich.edu    typedef IobParams Params;
1273576Sgblack@eecs.umich.edu    Iob(const Params *p);
1283576Sgblack@eecs.umich.edu
1293576Sgblack@eecs.umich.edu    const Params *
1303576Sgblack@eecs.umich.edu    params() const
1313576Sgblack@eecs.umich.edu    {
1323576Sgblack@eecs.umich.edu        return dynamic_cast<const Params *>(_params);
1333576Sgblack@eecs.umich.edu    }
1343576Sgblack@eecs.umich.edu
1353576Sgblack@eecs.umich.edu    Tick read(PacketPtr pkt) override;
1363576Sgblack@eecs.umich.edu    Tick write(PacketPtr pkt) override;
1373576Sgblack@eecs.umich.edu    void generateIpi(Type type, int cpu_id, int vector);
1383576Sgblack@eecs.umich.edu    void receiveDeviceInterrupt(DeviceId devid);
1393573Sgblack@eecs.umich.edu    bool receiveJBusInterrupt(int cpu_id, int source, uint64_t d0,
1403573Sgblack@eecs.umich.edu                              uint64_t d1);
1413573Sgblack@eecs.umich.edu
1423573Sgblack@eecs.umich.edu    AddrRangeList getAddrRanges() const override;
1434695Sgblack@eecs.umich.edu
1442221SN/A    void serialize(CheckpointOut &cp) const override;
1452221SN/A    void unserialize(CheckpointIn &cp) override;
1463576Sgblack@eecs.umich.edu};
1473576Sgblack@eecs.umich.edu
1483576Sgblack@eecs.umich.edu#endif //__DEV_SPARC_IOB_HH__
1493576Sgblack@eecs.umich.edu
1503576Sgblack@eecs.umich.edu