T1000.py revision 4104 
15425Sgblack@eecs.umich.edufrom m5.params import *
24298Sgblack@eecs.umich.edufrom m5.proxy import *
34298Sgblack@eecs.umich.edufrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
47087Snate@binkert.orgfrom Uart import Uart8250
57087Snate@binkert.orgfrom Platform import Platform
67087Snate@binkert.orgfrom SimConsole import SimConsole
77087Snate@binkert.org
87087Snate@binkert.org
97087Snate@binkert.orgclass MmDisk(BasicPioDevice):
107087Snate@binkert.org    type = 'MmDisk'
117087Snate@binkert.org    image = Param.DiskImage("Disk Image")
124298Sgblack@eecs.umich.edu    pio_addr = 0x1F40000000
137087Snate@binkert.org
147087Snate@binkert.orgclass DumbTOD(BasicPioDevice):
157087Snate@binkert.org    type = 'DumbTOD'
167087Snate@binkert.org    time = Param.Time('01/01/2009', "System time to use ('Now' for real time)")
177087Snate@binkert.org    pio_addr = 0xfff0c1fff8
187087Snate@binkert.org
197087Snate@binkert.orgclass Iob(PioDevice):
207087Snate@binkert.org    type = 'Iob'
214298Sgblack@eecs.umich.edu    pio_latency = Param.Latency('1ns', "Programed IO latency in simticks")
227087Snate@binkert.org
234298Sgblack@eecs.umich.edu
244298Sgblack@eecs.umich.educlass T1000(Platform):
254298Sgblack@eecs.umich.edu    type = 'T1000'
264298Sgblack@eecs.umich.edu    system = Param.System(Parent.any, "system")
274298Sgblack@eecs.umich.edu
284298Sgblack@eecs.umich.edu    fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000)
294298Sgblack@eecs.umich.edu            #warn_access="Accessing Clock Unit -- Unimplemented!")
304298Sgblack@eecs.umich.edu
314298Sgblack@eecs.umich.edu    fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384,
324298Sgblack@eecs.umich.edu            ret_data64=0x0000000000000000, update_data=False)
334298Sgblack@eecs.umich.edu            #warn_access="Accessing Memory Banks -- Unimplemented!")
344298Sgblack@eecs.umich.edu
354298Sgblack@eecs.umich.edu    fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000)
364298Sgblack@eecs.umich.edu            #warn_access="Accessing JBI -- Unimplemented!")
374298Sgblack@eecs.umich.edu
384338Sgblack@eecs.umich.edu    fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8,
394338Sgblack@eecs.umich.edu            ret_data64=0x0000000000000001, update_data=True)
404338Sgblack@eecs.umich.edu            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
415083Sgblack@eecs.umich.edu
425083Sgblack@eecs.umich.edu    fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8,
435083Sgblack@eecs.umich.edu            ret_data64=0x0000000000000001, update_data=True)
444524Sgblack@eecs.umich.edu            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
454524Sgblack@eecs.umich.edu
464524Sgblack@eecs.umich.edu    fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8,
474524Sgblack@eecs.umich.edu            ret_data64=0x0000000000000001, update_data=True)
484524Sgblack@eecs.umich.edu            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
494524Sgblack@eecs.umich.edu
504561Sgblack@eecs.umich.edu    fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8,
514561Sgblack@eecs.umich.edu            ret_data64=0x0000000000000001, update_data=True)
524561Sgblack@eecs.umich.edu            #warn_access="Accessing L2 Cache Banks -- Unimplemented!")
536516Sgblack@eecs.umich.edu
546516Sgblack@eecs.umich.edu    fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8,
556516Sgblack@eecs.umich.edu            ret_data64=0x0000000000000000, update_data=True)
565661Sgblack@eecs.umich.edu            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
575661Sgblack@eecs.umich.edu
585661Sgblack@eecs.umich.edu    fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8,
594519Sgblack@eecs.umich.edu            ret_data64=0x0000000000000000, update_data=True)
604519Sgblack@eecs.umich.edu            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
615425Sgblack@eecs.umich.edu
625425Sgblack@eecs.umich.edu    fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8,
635425Sgblack@eecs.umich.edu            ret_data64=0x0000000000000000, update_data=True)
64            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
65
66    fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8,
67            ret_data64=0x0000000000000000, update_data=True)
68            #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!")
69
70    fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
71            #warn_access="Accessing SSI -- Unimplemented!")
72
73    hconsole = SimConsole()
74    hvuart = Uart8250(pio_addr=0xfff0c2c000)
75    htod = DumbTOD()
76
77    pconsole = SimConsole()
78    puart0 = Uart8250(pio_addr=0x1f10000000)
79
80    iob = Iob()
81    # Attach I/O devices that are on chip
82    def attachOnChipIO(self, bus):
83        self.iob.pio = bus.port
84        self.htod.pio = bus.port
85
86
87    # Attach I/O devices to specified bus object.  Can't do this
88    # earlier, since the bus object itself is typically defined at the
89    # System level.
90    def attachIO(self, bus):
91        self.hvuart.sim_console = self.hconsole
92        self.puart0.sim_console = self.pconsole
93        self.fake_clk.pio = bus.port
94        self.fake_membnks.pio = bus.port
95        self.fake_l2_1.pio = bus.port
96        self.fake_l2_2.pio = bus.port
97        self.fake_l2_3.pio = bus.port
98        self.fake_l2_4.pio = bus.port
99        self.fake_l2esr_1.pio = bus.port
100        self.fake_l2esr_2.pio = bus.port
101        self.fake_l2esr_3.pio = bus.port
102        self.fake_l2esr_4.pio = bus.port
103        self.fake_ssi.pio = bus.port
104        self.fake_jbi.pio = bus.port
105        self.puart0.pio = bus.port
106        self.hvuart.pio = bus.port
107