T1000.py revision 4104
17202Sgblack@eecs.umich.edufrom m5.params import * 27202Sgblack@eecs.umich.edufrom m5.proxy import * 37202Sgblack@eecs.umich.edufrom Device import BasicPioDevice, PioDevice, IsaFake, BadAddr 47202Sgblack@eecs.umich.edufrom Uart import Uart8250 57202Sgblack@eecs.umich.edufrom Platform import Platform 67202Sgblack@eecs.umich.edufrom SimConsole import SimConsole 77202Sgblack@eecs.umich.edu 87202Sgblack@eecs.umich.edu 97202Sgblack@eecs.umich.educlass MmDisk(BasicPioDevice): 107202Sgblack@eecs.umich.edu type = 'MmDisk' 117202Sgblack@eecs.umich.edu image = Param.DiskImage("Disk Image") 127202Sgblack@eecs.umich.edu pio_addr = 0x1F40000000 137202Sgblack@eecs.umich.edu 147202Sgblack@eecs.umich.educlass DumbTOD(BasicPioDevice): 157202Sgblack@eecs.umich.edu type = 'DumbTOD' 167202Sgblack@eecs.umich.edu time = Param.Time('01/01/2009', "System time to use ('Now' for real time)") 177202Sgblack@eecs.umich.edu pio_addr = 0xfff0c1fff8 187202Sgblack@eecs.umich.edu 197202Sgblack@eecs.umich.educlass Iob(PioDevice): 207202Sgblack@eecs.umich.edu type = 'Iob' 217202Sgblack@eecs.umich.edu pio_latency = Param.Latency('1ns', "Programed IO latency in simticks") 227202Sgblack@eecs.umich.edu 237202Sgblack@eecs.umich.edu 247202Sgblack@eecs.umich.educlass T1000(Platform): 257202Sgblack@eecs.umich.edu type = 'T1000' 267202Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system") 277202Sgblack@eecs.umich.edu 287202Sgblack@eecs.umich.edu fake_clk = IsaFake(pio_addr=0x9600000000, pio_size=0x100000000) 297202Sgblack@eecs.umich.edu #warn_access="Accessing Clock Unit -- Unimplemented!") 307202Sgblack@eecs.umich.edu 317202Sgblack@eecs.umich.edu fake_membnks = IsaFake(pio_addr=0x9700000000, pio_size=16384, 327202Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=False) 337202Sgblack@eecs.umich.edu #warn_access="Accessing Memory Banks -- Unimplemented!") 347202Sgblack@eecs.umich.edu 357202Sgblack@eecs.umich.edu fake_jbi = IsaFake(pio_addr=0x8000000000, pio_size=0x100000000) 367202Sgblack@eecs.umich.edu #warn_access="Accessing JBI -- Unimplemented!") 377202Sgblack@eecs.umich.edu 387202Sgblack@eecs.umich.edu fake_l2_1 = IsaFake(pio_addr=0xA900000000, pio_size=0x8, 397202Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 407202Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 417202Sgblack@eecs.umich.edu 427202Sgblack@eecs.umich.edu fake_l2_2 = IsaFake(pio_addr=0xA900000040, pio_size=0x8, 437202Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 447202Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 457202Sgblack@eecs.umich.edu 467202Sgblack@eecs.umich.edu fake_l2_3 = IsaFake(pio_addr=0xA900000080, pio_size=0x8, 477202Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 487202Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 497202Sgblack@eecs.umich.edu 507202Sgblack@eecs.umich.edu fake_l2_4 = IsaFake(pio_addr=0xA9000000C0, pio_size=0x8, 517202Sgblack@eecs.umich.edu ret_data64=0x0000000000000001, update_data=True) 527202Sgblack@eecs.umich.edu #warn_access="Accessing L2 Cache Banks -- Unimplemented!") 537202Sgblack@eecs.umich.edu 547202Sgblack@eecs.umich.edu fake_l2esr_1 = IsaFake(pio_addr=0xAB00000000, pio_size=0x8, 557202Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 567202Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 577202Sgblack@eecs.umich.edu 587202Sgblack@eecs.umich.edu fake_l2esr_2 = IsaFake(pio_addr=0xAB00000040, pio_size=0x8, 597202Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 607202Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 617202Sgblack@eecs.umich.edu 627202Sgblack@eecs.umich.edu fake_l2esr_3 = IsaFake(pio_addr=0xAB00000080, pio_size=0x8, 637202Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 647202Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 657202Sgblack@eecs.umich.edu 667202Sgblack@eecs.umich.edu fake_l2esr_4 = IsaFake(pio_addr=0xAB000000C0, pio_size=0x8, 677202Sgblack@eecs.umich.edu ret_data64=0x0000000000000000, update_data=True) 687202Sgblack@eecs.umich.edu #warn_access="Accessing L2 ESR Cache Banks -- Unimplemented!") 697202Sgblack@eecs.umich.edu 707202Sgblack@eecs.umich.edu fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) 717202Sgblack@eecs.umich.edu #warn_access="Accessing SSI -- Unimplemented!") 727202Sgblack@eecs.umich.edu 737202Sgblack@eecs.umich.edu hconsole = SimConsole() 747202Sgblack@eecs.umich.edu hvuart = Uart8250(pio_addr=0xfff0c2c000) 757202Sgblack@eecs.umich.edu htod = DumbTOD() 767202Sgblack@eecs.umich.edu 777202Sgblack@eecs.umich.edu pconsole = SimConsole() 787202Sgblack@eecs.umich.edu puart0 = Uart8250(pio_addr=0x1f10000000) 797202Sgblack@eecs.umich.edu 807202Sgblack@eecs.umich.edu iob = Iob() 817202Sgblack@eecs.umich.edu # Attach I/O devices that are on chip 827202Sgblack@eecs.umich.edu def attachOnChipIO(self, bus): 837202Sgblack@eecs.umich.edu self.iob.pio = bus.port 847202Sgblack@eecs.umich.edu self.htod.pio = bus.port 857202Sgblack@eecs.umich.edu 867202Sgblack@eecs.umich.edu 877202Sgblack@eecs.umich.edu # Attach I/O devices to specified bus object. Can't do this 887202Sgblack@eecs.umich.edu # earlier, since the bus object itself is typically defined at the 897202Sgblack@eecs.umich.edu # System level. 907202Sgblack@eecs.umich.edu def attachIO(self, bus): 917202Sgblack@eecs.umich.edu self.hvuart.sim_console = self.hconsole 927202Sgblack@eecs.umich.edu self.puart0.sim_console = self.pconsole 937202Sgblack@eecs.umich.edu self.fake_clk.pio = bus.port 947202Sgblack@eecs.umich.edu self.fake_membnks.pio = bus.port 957202Sgblack@eecs.umich.edu self.fake_l2_1.pio = bus.port 967202Sgblack@eecs.umich.edu self.fake_l2_2.pio = bus.port 977202Sgblack@eecs.umich.edu self.fake_l2_3.pio = bus.port 987202Sgblack@eecs.umich.edu self.fake_l2_4.pio = bus.port 997202Sgblack@eecs.umich.edu self.fake_l2esr_1.pio = bus.port 1007202Sgblack@eecs.umich.edu self.fake_l2esr_2.pio = bus.port 101 self.fake_l2esr_3.pio = bus.port 102 self.fake_l2esr_4.pio = bus.port 103 self.fake_ssi.pio = bus.port 104 self.fake_jbi.pio = bus.port 105 self.puart0.pio = bus.port 106 self.hvuart.pio = bus.port 107