112239Sandreas.sandberg@arm.com/* 212239Sandreas.sandberg@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 312239Sandreas.sandberg@arm.com * All rights reserved. 412239Sandreas.sandberg@arm.com * 512239Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 612239Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 712239Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 812239Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 912239Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 1012239Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 1112239Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 1212239Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 1312239Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 1412239Sandreas.sandberg@arm.com * this software without specific prior written permission. 1512239Sandreas.sandberg@arm.com * 1612239Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712239Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812239Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912239Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012239Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112239Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212239Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312239Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412239Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512239Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612239Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712239Sandreas.sandberg@arm.com * 2812239Sandreas.sandberg@arm.com * Authors: Ali Saidi 2912239Sandreas.sandberg@arm.com */ 3012239Sandreas.sandberg@arm.com 3112239Sandreas.sandberg@arm.com/** @file 3212239Sandreas.sandberg@arm.com * Defines a 8250 UART 3312239Sandreas.sandberg@arm.com */ 3412239Sandreas.sandberg@arm.com 3512239Sandreas.sandberg@arm.com#ifndef __DEV_UART8250_HH__ 3612239Sandreas.sandberg@arm.com#define __DEV_UART8250_HH__ 3712239Sandreas.sandberg@arm.com 3812239Sandreas.sandberg@arm.com#include "dev/io_device.hh" 3912239Sandreas.sandberg@arm.com#include "dev/serial/uart.hh" 4012239Sandreas.sandberg@arm.com#include "params/Uart8250.hh" 4112239Sandreas.sandberg@arm.com 4212239Sandreas.sandberg@arm.com/* UART8250 Interrupt ID Register 4312239Sandreas.sandberg@arm.com * bit 0 Interrupt Pending 0 = true, 1 = false 4412239Sandreas.sandberg@arm.com * bit 2:1 ID of highest priority interrupt 4512239Sandreas.sandberg@arm.com * bit 7:3 zeroes 4612239Sandreas.sandberg@arm.com */ 4712239Sandreas.sandberg@arm.comconst uint8_t IIR_NOPEND = 0x1; 4812239Sandreas.sandberg@arm.com 4912239Sandreas.sandberg@arm.com// Interrupt IDs 5012239Sandreas.sandberg@arm.comconst uint8_t IIR_MODEM = 0x00; /* Modem Status (lowest priority) */ 5112239Sandreas.sandberg@arm.comconst uint8_t IIR_TXID = 0x02; /* Tx Data */ 5212239Sandreas.sandberg@arm.comconst uint8_t IIR_RXID = 0x04; /* Rx Data */ 5312239Sandreas.sandberg@arm.comconst uint8_t IIR_LINE = 0x06; /* Rx Line Status (highest priority)*/ 5412239Sandreas.sandberg@arm.com 5512239Sandreas.sandberg@arm.comconst uint8_t UART_IER_RDI = 0x01; 5612239Sandreas.sandberg@arm.comconst uint8_t UART_IER_THRI = 0x02; 5712239Sandreas.sandberg@arm.comconst uint8_t UART_IER_RLSI = 0x04; 5812239Sandreas.sandberg@arm.com 5912239Sandreas.sandberg@arm.com 6012239Sandreas.sandberg@arm.comconst uint8_t UART_LSR_TEMT = 0x40; 6112239Sandreas.sandberg@arm.comconst uint8_t UART_LSR_THRE = 0x20; 6212239Sandreas.sandberg@arm.comconst uint8_t UART_LSR_DR = 0x01; 6312239Sandreas.sandberg@arm.com 6412239Sandreas.sandberg@arm.comconst uint8_t UART_MCR_LOOP = 0x10; 6512239Sandreas.sandberg@arm.com 6612239Sandreas.sandberg@arm.com 6712239Sandreas.sandberg@arm.comclass Terminal; 6812239Sandreas.sandberg@arm.comclass Platform; 6912239Sandreas.sandberg@arm.com 7012239Sandreas.sandberg@arm.comclass Uart8250 : public Uart 7112239Sandreas.sandberg@arm.com{ 7212239Sandreas.sandberg@arm.com protected: 7312239Sandreas.sandberg@arm.com uint8_t IER, DLAB, LCR, MCR; 7412239Sandreas.sandberg@arm.com Tick lastTxInt; 7512239Sandreas.sandberg@arm.com 7612239Sandreas.sandberg@arm.com void processIntrEvent(int intrBit); 7712239Sandreas.sandberg@arm.com void scheduleIntr(Event *event); 7812239Sandreas.sandberg@arm.com 7912239Sandreas.sandberg@arm.com EventFunctionWrapper txIntrEvent; 8012239Sandreas.sandberg@arm.com EventFunctionWrapper rxIntrEvent; 8112239Sandreas.sandberg@arm.com 8212239Sandreas.sandberg@arm.com public: 8312239Sandreas.sandberg@arm.com typedef Uart8250Params Params; 8412239Sandreas.sandberg@arm.com const Params * 8512239Sandreas.sandberg@arm.com params() const 8612239Sandreas.sandberg@arm.com { 8712239Sandreas.sandberg@arm.com return dynamic_cast<const Params *>(_params); 8812239Sandreas.sandberg@arm.com } 8912239Sandreas.sandberg@arm.com Uart8250(const Params *p); 9012239Sandreas.sandberg@arm.com 9112239Sandreas.sandberg@arm.com Tick read(PacketPtr pkt) override; 9212239Sandreas.sandberg@arm.com Tick write(PacketPtr pkt) override; 9312239Sandreas.sandberg@arm.com AddrRangeList getAddrRanges() const override; 9412239Sandreas.sandberg@arm.com 9512239Sandreas.sandberg@arm.com /** 9612239Sandreas.sandberg@arm.com * Inform the uart that there is data available. 9712239Sandreas.sandberg@arm.com */ 9812239Sandreas.sandberg@arm.com void dataAvailable() override; 9912239Sandreas.sandberg@arm.com 10012239Sandreas.sandberg@arm.com 10112239Sandreas.sandberg@arm.com /** 10212239Sandreas.sandberg@arm.com * Return if we have an interrupt pending 10312239Sandreas.sandberg@arm.com * @return interrupt status 10412239Sandreas.sandberg@arm.com */ 10512239Sandreas.sandberg@arm.com virtual bool intStatus() { return status ? true : false; } 10612239Sandreas.sandberg@arm.com 10712239Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const override; 10812239Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) override; 10912239Sandreas.sandberg@arm.com}; 11012239Sandreas.sandberg@arm.com 11112239Sandreas.sandberg@arm.com#endif // __TSUNAMI_UART_HH__ 112