pcireg.h revision 2846
110066Sandreas.hansson@arm.com/* 210066Sandreas.hansson@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 310066Sandreas.hansson@arm.com * All rights reserved. 410066Sandreas.hansson@arm.com * 510066Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 610066Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 710066Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 810066Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 910066Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 1010066Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1110066Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 1210066Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 1310066Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 1410066Sandreas.hansson@arm.com * this software without specific prior written permission. 1510066Sandreas.hansson@arm.com * 1610066Sandreas.hansson@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710066Sandreas.hansson@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810066Sandreas.hansson@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910066Sandreas.hansson@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010066Sandreas.hansson@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110066Sandreas.hansson@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210066Sandreas.hansson@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310066Sandreas.hansson@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410066Sandreas.hansson@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510066Sandreas.hansson@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610066Sandreas.hansson@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710066Sandreas.hansson@arm.com * 2810066Sandreas.hansson@arm.com * Authors: Nathan Binkert 2910066Sandreas.hansson@arm.com * Miguel Serrano 3010066Sandreas.hansson@arm.com */ 3110066Sandreas.hansson@arm.com 3210066Sandreas.hansson@arm.com/* @file 3310066Sandreas.hansson@arm.com * Device register definitions for a device's PCI config space 3410066Sandreas.hansson@arm.com */ 3510066Sandreas.hansson@arm.com 3610066Sandreas.hansson@arm.com#ifndef __PCIREG_H__ 3710066Sandreas.hansson@arm.com#define __PCIREG_H__ 3810066Sandreas.hansson@arm.com 3910066Sandreas.hansson@arm.com#include <sys/types.h> 4010066Sandreas.hansson@arm.com 4110066Sandreas.hansson@arm.comunion PCIConfig { 4210066Sandreas.hansson@arm.com uint8_t data[64]; 4310066Sandreas.hansson@arm.com 4410066Sandreas.hansson@arm.com struct { 4510066Sandreas.hansson@arm.com uint16_t vendor; 4610066Sandreas.hansson@arm.com uint16_t device; 4710066Sandreas.hansson@arm.com uint16_t command; 4810066Sandreas.hansson@arm.com uint16_t status; 4910066Sandreas.hansson@arm.com uint8_t revision; 5010066Sandreas.hansson@arm.com uint8_t progIF; 5110066Sandreas.hansson@arm.com uint8_t subClassCode; 5210066Sandreas.hansson@arm.com uint8_t classCode; 5310066Sandreas.hansson@arm.com uint8_t cacheLineSize; 5410066Sandreas.hansson@arm.com uint8_t latencyTimer; 5510066Sandreas.hansson@arm.com uint8_t headerType; 5610066Sandreas.hansson@arm.com uint8_t bist; 5710066Sandreas.hansson@arm.com union { 5810066Sandreas.hansson@arm.com uint32_t baseAddr[6]; 5910066Sandreas.hansson@arm.com 6010066Sandreas.hansson@arm.com struct { 6110066Sandreas.hansson@arm.com uint32_t baseAddr0; 6210066Sandreas.hansson@arm.com uint32_t baseAddr1; 6310066Sandreas.hansson@arm.com uint32_t baseAddr2; 6410066Sandreas.hansson@arm.com uint32_t baseAddr3; 6510066Sandreas.hansson@arm.com uint32_t baseAddr4; 6610066Sandreas.hansson@arm.com uint32_t baseAddr5; 6710066Sandreas.hansson@arm.com }; 6810066Sandreas.hansson@arm.com }; 6910066Sandreas.hansson@arm.com uint32_t cardbusCIS; 7010066Sandreas.hansson@arm.com uint16_t subsystemVendorID; 7110066Sandreas.hansson@arm.com uint16_t subsystemID; 7210066Sandreas.hansson@arm.com uint32_t expansionROM; 7310066Sandreas.hansson@arm.com uint32_t reserved0; 7410066Sandreas.hansson@arm.com uint32_t reserved1; 7510066Sandreas.hansson@arm.com uint8_t interruptLine; 7610066Sandreas.hansson@arm.com uint8_t interruptPin; 7710066Sandreas.hansson@arm.com uint8_t minimumGrant; 7810066Sandreas.hansson@arm.com uint8_t maximumLatency; 7910066Sandreas.hansson@arm.com }; 8010066Sandreas.hansson@arm.com}; 8110066Sandreas.hansson@arm.com 8210066Sandreas.hansson@arm.com// Common PCI offsets 8310066Sandreas.hansson@arm.com#define PCI_VENDOR_ID 0x00 // Vendor ID ro 8410066Sandreas.hansson@arm.com#define PCI_DEVICE_ID 0x02 // Device ID ro 8510066Sandreas.hansson@arm.com#define PCI_COMMAND 0x04 // Command rw 8610066Sandreas.hansson@arm.com#define PCI_STATUS 0x06 // Status rw 8710066Sandreas.hansson@arm.com#define PCI_REVISION_ID 0x08 // Revision ID ro 8810066Sandreas.hansson@arm.com#define PCI_CLASS_CODE 0x09 // Class Code ro 8910066Sandreas.hansson@arm.com#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro 9010066Sandreas.hansson@arm.com#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro 9110066Sandreas.hansson@arm.com#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+ 9210066Sandreas.hansson@arm.com#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+ 9310066Sandreas.hansson@arm.com#define PCI_HEADER_TYPE 0x0E // Header Type ro 9410066Sandreas.hansson@arm.com#define PCI_BIST 0x0F // Built in self test rw 9510066Sandreas.hansson@arm.com 9610066Sandreas.hansson@arm.com// some pci command reg bitfields 9710066Sandreas.hansson@arm.com#define PCI_CMD_BME 0x04 // Bus master function enable 9810066Sandreas.hansson@arm.com#define PCI_CMD_MSE 0x02 // Memory Space Access enable 9910066Sandreas.hansson@arm.com#define PCI_CMD_IOSE 0x01 // I/O space enable 10010066Sandreas.hansson@arm.com 10110066Sandreas.hansson@arm.com// Type 0 PCI offsets 10210066Sandreas.hansson@arm.com#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw 10310066Sandreas.hansson@arm.com#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw 10410066Sandreas.hansson@arm.com#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw 10510066Sandreas.hansson@arm.com#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw 10610066Sandreas.hansson@arm.com#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw 10710066Sandreas.hansson@arm.com#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw 10810066Sandreas.hansson@arm.com#define PCI0_CIS 0x28 // CardBus CIS Pointer ro 10910066Sandreas.hansson@arm.com#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro 11010066Sandreas.hansson@arm.com#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro 11110066Sandreas.hansson@arm.com#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw 11210066Sandreas.hansson@arm.com#define PCI0_RESERVED0 0x34 11310066Sandreas.hansson@arm.com#define PCI0_RESERVED1 0x38 11410066Sandreas.hansson@arm.com#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw 11510066Sandreas.hansson@arm.com#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro 11610066Sandreas.hansson@arm.com#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro 11710066Sandreas.hansson@arm.com#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro 11810066Sandreas.hansson@arm.com 11910066Sandreas.hansson@arm.com// Type 1 PCI offsets 12010066Sandreas.hansson@arm.com#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw 12110066Sandreas.hansson@arm.com#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw 12210066Sandreas.hansson@arm.com#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw 12310066Sandreas.hansson@arm.com#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw 12410066Sandreas.hansson@arm.com#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw 12510066Sandreas.hansson@arm.com#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+ 12610066Sandreas.hansson@arm.com#define PCI1_IO_BASE 0x1C // I/O Base rw 12710066Sandreas.hansson@arm.com#define PCI1_IO_LIMIT 0x1D // I/O Limit rw 12810066Sandreas.hansson@arm.com#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw 12910066Sandreas.hansson@arm.com#define PCI1_MEM_BASE 0x20 // Memory Base rw 13010066Sandreas.hansson@arm.com#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw 13110066Sandreas.hansson@arm.com#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw 13210066Sandreas.hansson@arm.com#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw 13310066Sandreas.hansson@arm.com#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw 13410066Sandreas.hansson@arm.com#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw 13510066Sandreas.hansson@arm.com#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw 13610066Sandreas.hansson@arm.com#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw 13710066Sandreas.hansson@arm.com#define PCI1_RESERVED 0x34 // Reserved ro 13810066Sandreas.hansson@arm.com#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw 13910066Sandreas.hansson@arm.com#define PCI1_INTR_LINE 0x3C // Interrupt Line rw 14010066Sandreas.hansson@arm.com#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro 14110066Sandreas.hansson@arm.com#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw 14210066Sandreas.hansson@arm.com 14310066Sandreas.hansson@arm.com// Device specific offsets 14410066Sandreas.hansson@arm.com#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes 14510066Sandreas.hansson@arm.com#define PCI_CONFIG_SIZE 0xFF 14610066Sandreas.hansson@arm.com 14710066Sandreas.hansson@arm.com// Some Vendor IDs 14810066Sandreas.hansson@arm.com#define PCI_VENDOR_DEC 0x1011 14910066Sandreas.hansson@arm.com#define PCI_VENDOR_NCR 0x101A 15010066Sandreas.hansson@arm.com#define PCI_VENDOR_QLOGIC 0x1077 15110066Sandreas.hansson@arm.com#define PCI_VENDOR_SIMOS 0x1291 15210066Sandreas.hansson@arm.com 15310066Sandreas.hansson@arm.com// Some Product IDs 15410066Sandreas.hansson@arm.com#define PCI_PRODUCT_DEC_PZA 0x0008 15510066Sandreas.hansson@arm.com#define PCI_PRODUCT_NCR_810 0x0001 15610066Sandreas.hansson@arm.com#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 15710066Sandreas.hansson@arm.com#define PCI_PRODUCT_SIMOS_SIMOS 0x1291 15810066Sandreas.hansson@arm.com#define PCI_PRODUCT_SIMOS_ETHER 0x1292 15910066Sandreas.hansson@arm.com 16010066Sandreas.hansson@arm.com#endif // __PCIREG_H__ 16110066Sandreas.hansson@arm.com