pcireg.h revision 2
14123Sbinkertn@umich.edu/* 24123Sbinkertn@umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 34123Sbinkertn@umich.edu * All rights reserved. 44123Sbinkertn@umich.edu * 54123Sbinkertn@umich.edu * Redistribution and use in source and binary forms, with or without 64123Sbinkertn@umich.edu * modification, are permitted provided that the following conditions are 74123Sbinkertn@umich.edu * met: redistributions of source code must retain the above copyright 84123Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer; 94123Sbinkertn@umich.edu * redistributions in binary form must reproduce the above copyright 104123Sbinkertn@umich.edu * notice, this list of conditions and the following disclaimer in the 114123Sbinkertn@umich.edu * documentation and/or other materials provided with the distribution; 124123Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 134123Sbinkertn@umich.edu * contributors may be used to endorse or promote products derived from 144123Sbinkertn@umich.edu * this software without specific prior written permission. 154123Sbinkertn@umich.edu * 164123Sbinkertn@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174123Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184123Sbinkertn@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194123Sbinkertn@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204123Sbinkertn@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214123Sbinkertn@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224123Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234123Sbinkertn@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244123Sbinkertn@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254123Sbinkertn@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264123Sbinkertn@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274123Sbinkertn@umich.edu */ 284123Sbinkertn@umich.edu 294123Sbinkertn@umich.edu/* @file 304123Sbinkertn@umich.edu * Device register definitions for a device's PCI config space 314123Sbinkertn@umich.edu */ 324123Sbinkertn@umich.edu 334123Sbinkertn@umich.edu#ifndef __PCIREG_H__ 344123Sbinkertn@umich.edu#define __PCIREG_H__ 354123Sbinkertn@umich.edu 364123Sbinkertn@umich.edu#include <sys/types.h> 374123Sbinkertn@umich.edu 384123Sbinkertn@umich.eduunion PCIConfig { 394123Sbinkertn@umich.edu uint8_t data[64]; 404123Sbinkertn@umich.edu 414123Sbinkertn@umich.edu struct hdr { 424123Sbinkertn@umich.edu uint16_t vendor; 434123Sbinkertn@umich.edu uint16_t device; 444123Sbinkertn@umich.edu uint16_t command; 454123Sbinkertn@umich.edu uint16_t status; 464123Sbinkertn@umich.edu uint8_t revision; 474123Sbinkertn@umich.edu uint8_t progIF; 484123Sbinkertn@umich.edu uint8_t subClassCode; 494123Sbinkertn@umich.edu uint8_t classCode; 504123Sbinkertn@umich.edu uint8_t cacheLineSize; 514123Sbinkertn@umich.edu uint8_t latencyTimer; 524123Sbinkertn@umich.edu uint8_t headerType; 534123Sbinkertn@umich.edu uint8_t bist; 544123Sbinkertn@umich.edu 554123Sbinkertn@umich.edu union { 564123Sbinkertn@umich.edu struct { 574123Sbinkertn@umich.edu uint32_t baseAddr0; 584123Sbinkertn@umich.edu uint32_t baseAddr1; 594123Sbinkertn@umich.edu uint32_t baseAddr2; 604123Sbinkertn@umich.edu uint32_t baseAddr3; 614123Sbinkertn@umich.edu uint32_t baseAddr4; 624123Sbinkertn@umich.edu uint32_t baseAddr5; 634123Sbinkertn@umich.edu uint32_t cardbusCIS; 644123Sbinkertn@umich.edu uint16_t subsystemVendorID; 654123Sbinkertn@umich.edu uint16_t subsystemID; 664123Sbinkertn@umich.edu uint32_t expansionROM; 674123Sbinkertn@umich.edu uint32_t reserved0; 684123Sbinkertn@umich.edu uint32_t reserved1; 694123Sbinkertn@umich.edu uint8_t interruptLine; 704123Sbinkertn@umich.edu uint8_t interruptPin; 714123Sbinkertn@umich.edu uint8_t minimumGrant; 724123Sbinkertn@umich.edu uint8_t maximumLatency; 734123Sbinkertn@umich.edu } pci0; 744123Sbinkertn@umich.edu 754123Sbinkertn@umich.edu struct { 764123Sbinkertn@umich.edu uint32_t baseAddr0; 77 uint32_t baseAddr1; 78 uint8_t priBusNum; 79 uint8_t secBusNum; 80 uint8_t subBusNum; 81 uint8_t secLatency; 82 uint8_t ioBase; 83 uint8_t minimumGrantioLimit; 84 uint16_t secStatus; 85 uint16_t memBase; 86 uint16_t memLimit; 87 uint16_t prefetchMemBase; 88 uint16_t prefetchMemLimit; 89 uint32_t prfBaseUpper32; 90 uint32_t prfLimitUpper32; 91 uint16_t ioBaseUpper16; 92 uint16_t ioLimitUpper16; 93 uint32_t reserved0; 94 uint32_t expansionROM; 95 uint8_t interruptLine; 96 uint8_t interruptPin; 97 uint16_t bridgeControl; 98 } pci1; 99 }; 100 } hdr; 101}; 102 103// Common PCI offsets 104#define PCI_VENDOR_ID 0x00 // Vendor ID ro 105#define PCI_DEVICE_ID 0x02 // Device ID ro 106#define PCI_COMMAND 0x04 // Command rw 107#define PCI_STATUS 0x06 // Status rw 108#define PCI_REVISION_ID 0x08 // Revision ID ro 109#define PCI_CLASS_CODE 0x09 // Class Code ro 110#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro 111#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro 112#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+ 113#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+ 114#define PCI_HEADER_TYPE 0x0E // Header Type ro 115#define PCI_BIST 0x0F // Built in self test rw 116 117// Type 0 PCI offsets 118#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw 119#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw 120#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw 121#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw 122#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw 123#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw 124#define PCI0_CIS 0x28 // CardBus CIS Pointer ro 125#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro 126#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro 127#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw 128#define PCI0_RESERVED0 0x34 129#define PCI0_RESERVED1 0x38 130#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw 131#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro 132#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro 133#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro 134 135// Type 1 PCI offsets 136#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw 137#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw 138#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw 139#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw 140#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw 141#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+ 142#define PCI1_IO_BASE 0x1C // I/O Base rw 143#define PCI1_IO_LIMIT 0x1D // I/O Limit rw 144#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw 145#define PCI1_MEM_BASE 0x20 // Memory Base rw 146#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw 147#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw 148#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw 149#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw 150#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw 151#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw 152#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw 153#define PCI1_RESERVED 0x34 // Reserved ro 154#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw 155#define PCI1_INTR_LINE 0x3C // Interrupt Line rw 156#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro 157#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw 158 159// Device specific offsets 160#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes 161 162// Some Vendor IDs 163#define PCI_VENDOR_DEC 0x1011 164#define PCI_VENDOR_NCR 0x101A 165#define PCI_VENDOR_QLOGIC 0x1077 166#define PCI_VENDOR_SIMOS 0x1291 167 168// Some Product IDs 169#define PCI_PRODUCT_DEC_PZA 0x0008 170#define PCI_PRODUCT_NCR_810 0x0001 171#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020 172#define PCI_PRODUCT_SIMOS_SIMOS 0x1291 173#define PCI_PRODUCT_SIMOS_ETHER 0x1292 174 175#endif // __PCIREG_H__ 176