device.cc revision 793
12357Sktlim@umich.edu/* 22357Sktlim@umich.edu * Copyright (c) 2003 The Regents of The University of Michigan 32357Sktlim@umich.edu * All rights reserved. 42357Sktlim@umich.edu * 52357Sktlim@umich.edu * Redistribution and use in source and binary forms, with or without 62357Sktlim@umich.edu * modification, are permitted provided that the following conditions are 72357Sktlim@umich.edu * met: redistributions of source code must retain the above copyright 82357Sktlim@umich.edu * notice, this list of conditions and the following disclaimer; 92357Sktlim@umich.edu * redistributions in binary form must reproduce the above copyright 102357Sktlim@umich.edu * notice, this list of conditions and the following disclaimer in the 112357Sktlim@umich.edu * documentation and/or other materials provided with the distribution; 122357Sktlim@umich.edu * neither the name of the copyright holders nor the names of its 132357Sktlim@umich.edu * contributors may be used to endorse or promote products derived from 142357Sktlim@umich.edu * this software without specific prior written permission. 152357Sktlim@umich.edu * 162357Sktlim@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172357Sktlim@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182357Sktlim@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192357Sktlim@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202357Sktlim@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212357Sktlim@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222357Sktlim@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232357Sktlim@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242357Sktlim@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252357Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262357Sktlim@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272357Sktlim@umich.edu */ 282357Sktlim@umich.edu 292357Sktlim@umich.edu/* @file 302357Sktlim@umich.edu * A single PCI device configuration space entry. 312357Sktlim@umich.edu */ 322357Sktlim@umich.edu 332357Sktlim@umich.edu#include <list> 342357Sktlim@umich.edu#include <sstream> 352357Sktlim@umich.edu#include <string> 362357Sktlim@umich.edu#include <vector> 372357Sktlim@umich.edu 382357Sktlim@umich.edu#include "base/inifile.hh" 392357Sktlim@umich.edu#include "base/misc.hh" 402357Sktlim@umich.edu#include "base/str.hh" // for to_number 412357Sktlim@umich.edu#include "base/trace.hh" 422357Sktlim@umich.edu#include "dev/pciareg.h" 432357Sktlim@umich.edu#include "dev/scsi_ctrl.hh" 442357Sktlim@umich.edu#include "dev/pcidev.hh" 452357Sktlim@umich.edu#include "dev/pciconfigall.hh" 462357Sktlim@umich.edu#include "mem/functional_mem/memory_control.hh" 472357Sktlim@umich.edu#include "sim/builder.hh" 482357Sktlim@umich.edu#include "sim/param.hh" 492357Sktlim@umich.edu#include "sim/universe.hh" 502357Sktlim@umich.edu 512357Sktlim@umich.eduusing namespace std; 522357Sktlim@umich.edu 532357Sktlim@umich.eduPciDev::PciDev(const string &name, PCIConfigAll *cf, uint32_t bus, 542357Sktlim@umich.edu uint32_t dev, uint32_t func) 552357Sktlim@umich.edu : MMapDevice(name), ConfigSpace(cf), Bus(bus), Device(dev), Function(func) 562357Sktlim@umich.edu{ 572357Sktlim@umich.edu memset(config.data, 0, sizeof(config.data)); 582357Sktlim@umich.edu 592357Sktlim@umich.edu // Setup pointer in config space to point to this entry 602357Sktlim@umich.edu if(cf->devices[dev][func] != NULL) 612357Sktlim@umich.edu panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func); 622357Sktlim@umich.edu else 632357Sktlim@umich.edu cf->devices[dev][func] = this; 642357Sktlim@umich.edu} 652357Sktlim@umich.edu 662357Sktlim@umich.edu 672357Sktlim@umich.eduvoid 682357Sktlim@umich.eduPciDev::ReadConfig(int offset, int size, uint8_t *data) 692357Sktlim@umich.edu{ 702357Sktlim@umich.edu switch(size) { 712357Sktlim@umich.edu case sizeof(uint32_t): 722357Sktlim@umich.edu memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t)); 732357Sktlim@umich.edu DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n", 742357Sktlim@umich.edu Device, Function, offset, *(uint32_t*)(config.data + offset)); 752357Sktlim@umich.edu break; 762357Sktlim@umich.edu case sizeof(uint16_t): 772357Sktlim@umich.edu memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t)); 782357Sktlim@umich.edu DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n", 792357Sktlim@umich.edu Device, Function, offset, *(uint16_t*)(config.data + offset)); 802357Sktlim@umich.edu break; 812357Sktlim@umich.edu case sizeof(uint8_t): 822357Sktlim@umich.edu memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t)); 832357Sktlim@umich.edu printf("data: %#x\n", *(uint8_t*)(config.data + offset)); 842357Sktlim@umich.edu DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n", 852357Sktlim@umich.edu Device, Function, offset, *(uint8_t*)(config.data + offset)); 862357Sktlim@umich.edu break; 872357Sktlim@umich.edu default: 882357Sktlim@umich.edu panic("Invalid Read Size"); 892357Sktlim@umich.edu } 902357Sktlim@umich.edu} 912357Sktlim@umich.edu 922357Sktlim@umich.edu 932357Sktlim@umich.eduvoid 942357Sktlim@umich.eduPciDev::WriteConfig(int offset, int size, uint32_t data) 952357Sktlim@umich.edu{ 962357Sktlim@umich.edu union { 972357Sktlim@umich.edu uint8_t byte_value; 982357Sktlim@umich.edu uint16_t half_value; 992357Sktlim@umich.edu uint32_t word_value; 1002357Sktlim@umich.edu }; 1012357Sktlim@umich.edu word_value = data; 1022357Sktlim@umich.edu 1032357Sktlim@umich.edu DPRINTF(PCIDEV, "write device: %#x function: %#x register: %#x size: %#x data: %#x\n", 1042357Sktlim@umich.edu Device, Function, offset, size, word_value); 1052357Sktlim@umich.edu 1062357Sktlim@umich.edu switch (size) { 1072357Sktlim@umich.edu case sizeof(uint8_t): // 1-byte access 1082357Sktlim@umich.edu switch (offset) { 1092357Sktlim@umich.edu case PCI0_INTERRUPT_LINE: 1102357Sktlim@umich.edu case PCI_CACHE_LINE_SIZE: 1112357Sktlim@umich.edu *(uint8_t *)&config.data[offset] = byte_value; 1122357Sktlim@umich.edu break; 1132357Sktlim@umich.edu 1142357Sktlim@umich.edu default: 1152357Sktlim@umich.edu panic("writing to a read only register"); 1162357Sktlim@umich.edu } 1172357Sktlim@umich.edu break; 1182357Sktlim@umich.edu 1192357Sktlim@umich.edu case sizeof(uint16_t): // 2-byte access 1202357Sktlim@umich.edu switch (offset) { 1212357Sktlim@umich.edu case PCI_COMMAND: 1222357Sktlim@umich.edu case PCI_STATUS: 1232357Sktlim@umich.edu case PCI_CACHE_LINE_SIZE: 1242357Sktlim@umich.edu *(uint16_t *)&config.data[offset] = half_value; 1252357Sktlim@umich.edu break; 1262357Sktlim@umich.edu 1272357Sktlim@umich.edu default: 1282357Sktlim@umich.edu panic("writing to a read only register"); 1292357Sktlim@umich.edu } 1302357Sktlim@umich.edu break; 1312357Sktlim@umich.edu 1322357Sktlim@umich.edu case sizeof(uint16_t)+1: // 3-byte access 1332357Sktlim@umich.edu panic("invalid access size"); 1342357Sktlim@umich.edu 1352357Sktlim@umich.edu case sizeof(uint32_t): // 4-byte access 1362357Sktlim@umich.edu switch (offset) { 1372357Sktlim@umich.edu case PCI0_BASE_ADDR0: 1382357Sktlim@umich.edu case PCI0_BASE_ADDR1: 1392357Sktlim@umich.edu case PCI0_BASE_ADDR2: 1402357Sktlim@umich.edu case PCI0_BASE_ADDR3: 1412357Sktlim@umich.edu case PCI0_BASE_ADDR4: 1422357Sktlim@umich.edu case PCI0_BASE_ADDR5: 1432357Sktlim@umich.edu // Writing 0xffffffff to a BAR tells the card to set the value of the bar 1442357Sktlim@umich.edu // to size of memory it needs 1452357Sktlim@umich.edu if (word_value == 0xffffffff) { 1462357Sktlim@umich.edu // This is I/O Space, bottom two bits are read only 1472357Sktlim@umich.edu if(config.data[offset] & 0x1) { 1482357Sktlim@umich.edu *(uint32_t *)&config.data[offset] = 1492357Sktlim@umich.edu ~(BARSize[offset-PCI0_BASE_ADDR0] - 1) | (config.data[offset] & 0x3); 1502357Sktlim@umich.edu } else { 1512357Sktlim@umich.edu // This is memory space, bottom four bits are read only 1522357Sktlim@umich.edu *(uint32_t *)&config.data[offset] = 1532357Sktlim@umich.edu ~(BARSize[(offset-PCI0_BASE_ADDR0)>>2] - 1) | (config.data[offset] & 0xF); 1542357Sktlim@umich.edu } 1552357Sktlim@umich.edu 1562357Sktlim@umich.edu 1572357Sktlim@umich.edu } else { 1582357Sktlim@umich.edu // This is I/O Space, bottom two bits are read only 1592357Sktlim@umich.edu if(config.data[offset] & 0x1) { 1602357Sktlim@umich.edu *(uint32_t *)&config.data[offset] = (word_value & ~0x3) | 1612357Sktlim@umich.edu (config.data[offset] & 0x3); 1622357Sktlim@umich.edu } else { 1632357Sktlim@umich.edu // This is memory space, bottom four bits are read only 1642357Sktlim@umich.edu *(uint32_t *)&config.data[offset] = (word_value & ~0xF) | 1652357Sktlim@umich.edu (config.data[offset] & 0xF); 1662357Sktlim@umich.edu } 1672357Sktlim@umich.edu } 1682357Sktlim@umich.edu break; 1692357Sktlim@umich.edu case PCI0_ROM_BASE_ADDR: 1702357Sktlim@umich.edu if (word_value == 0xfffffffe) 1712357Sktlim@umich.edu *(uint32_t *)&config.data[offset] = 0xffffffff; 1722357Sktlim@umich.edu else 1732357Sktlim@umich.edu *(uint32_t *)&config.data[offset] = word_value; 1742357Sktlim@umich.edu break; 1752357Sktlim@umich.edu case PCI_COMMAND: 1762357Sktlim@umich.edu // This could also clear some of the error bits in the Status register 1772357Sktlim@umich.edu // However they should never get set, so lets ignore it for now 1782357Sktlim@umich.edu *(uint16_t *)&config.data[offset] = half_value; 1792357Sktlim@umich.edu break; 1802357Sktlim@umich.edu 1812357Sktlim@umich.edu 1822357Sktlim@umich.edu default: 1832357Sktlim@umich.edu panic("writing to a read only register"); 1842357Sktlim@umich.edu } 1852357Sktlim@umich.edu break; 1862357Sktlim@umich.edu } 1872357Sktlim@umich.edu 1882357Sktlim@umich.edu} 1892357Sktlim@umich.edu 1902357Sktlim@umich.eduvoid 1912357Sktlim@umich.eduPciDev::serialize(ostream &os) 1922357Sktlim@umich.edu{ 1932357Sktlim@umich.edu SERIALIZE_ARRAY(config.data, 64); 1942357Sktlim@umich.edu} 1952357Sktlim@umich.edu 1962357Sktlim@umich.eduvoid 1972357Sktlim@umich.eduPciDev::unserialize(Checkpoint *cp, const std::string §ion) 1982357Sktlim@umich.edu{ 1992357Sktlim@umich.edu UNSERIALIZE_ARRAY(config.data, 64); 2002357Sktlim@umich.edu} 2012357Sktlim@umich.edu 2022357Sktlim@umich.edu 2032357Sktlim@umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(PciDev) 2042357Sktlim@umich.edu 2052357Sktlim@umich.edu Param<int> VendorID; 2062357Sktlim@umich.edu Param<int> DeviceID; 2072357Sktlim@umich.edu Param<int> Command; 2082357Sktlim@umich.edu Param<int> Status; 2092357Sktlim@umich.edu Param<int> Revision; 2102357Sktlim@umich.edu Param<int> ProgIF; 2112357Sktlim@umich.edu Param<int> SubClassCode; 2122357Sktlim@umich.edu Param<int> ClassCode; 2132357Sktlim@umich.edu Param<int> CacheLineSize; 2142357Sktlim@umich.edu Param<int> LatencyTimer; 2152357Sktlim@umich.edu Param<int> HeaderType; 2162357Sktlim@umich.edu Param<int> BIST; 2172357Sktlim@umich.edu Param<uint32_t> BAR0; 2182357Sktlim@umich.edu Param<uint32_t> BAR1; 2192357Sktlim@umich.edu Param<uint32_t> BAR2; 2202357Sktlim@umich.edu Param<uint32_t> BAR3; 2212357Sktlim@umich.edu Param<uint32_t> BAR4; 2222357Sktlim@umich.edu Param<uint32_t> BAR5; 2232357Sktlim@umich.edu Param<uint32_t> CardbusCIS; 2242357Sktlim@umich.edu Param<int> SubsystemVendorID; 2252357Sktlim@umich.edu Param<int> SubsystemID; 2262357Sktlim@umich.edu Param<uint32_t> ExpansionROM; 2272357Sktlim@umich.edu Param<int> InterruptLine; 2282357Sktlim@umich.edu Param<int> InterruptPin; 2292357Sktlim@umich.edu Param<int> MinimumGrant; 2302357Sktlim@umich.edu Param<int> MaximumLatency; 2312357Sktlim@umich.edu Param<uint32_t> BAR0Size; 2322357Sktlim@umich.edu Param<uint32_t> BAR1Size; 2332357Sktlim@umich.edu Param<uint32_t> BAR2Size; 2342357Sktlim@umich.edu Param<uint32_t> BAR3Size; 2352357Sktlim@umich.edu Param<uint32_t> BAR4Size; 2362357Sktlim@umich.edu Param<uint32_t> BAR5Size; 2372357Sktlim@umich.edu 2382357Sktlim@umich.edu SimObjectParam<MemoryController *> mmu; 2392357Sktlim@umich.edu SimObjectParam<PCIConfigAll*> cf; 2402357Sktlim@umich.edu Param<Addr> addr; 2412357Sktlim@umich.edu Param<Addr> mask; 2422357Sktlim@umich.edu Param<uint32_t> bus; 2432357Sktlim@umich.edu Param<uint32_t> device; 2442357Sktlim@umich.edu Param<uint32_t> func; 2452357Sktlim@umich.edu 2462357Sktlim@umich.edu 2472357Sktlim@umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(PciDev) 2482357Sktlim@umich.edu 2492357Sktlim@umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(PciDev) 250 251 INIT_PARAM(VendorID, "Vendor ID"), 252 INIT_PARAM(DeviceID, "Device ID"), 253 INIT_PARAM_DFLT(Command, "Command Register", 0x00), 254 INIT_PARAM_DFLT(Status, "Status Register", 0x00), 255 INIT_PARAM_DFLT(Revision, "Device Revision", 0x00), 256 INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00), 257 INIT_PARAM(SubClassCode, "Sub-Class Code"), 258 INIT_PARAM(ClassCode, "Class Code"), 259 INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00), 260 INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00), 261 INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00), 262 INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00), 263 INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00), 264 INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00), 265 INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00), 266 INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00), 267 INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00), 268 INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00), 269 INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00), 270 INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00), 271 INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00), 272 INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00), 273 INIT_PARAM(InterruptLine, "Interrupt Line Register"), 274 INIT_PARAM(InterruptPin, "Interrupt Pin Register"), 275 INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00), 276 INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00), 277 INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00), 278 INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00), 279 INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00), 280 INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00), 281 INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00), 282 INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00), 283 284 INIT_PARAM(cf, "Pointer to Configspace device"), 285 INIT_PARAM(bus, "PCI Bus Number"), 286 INIT_PARAM(device, "PCI Device number"), 287 INIT_PARAM(func, "PCI Function Number") 288 289 290END_INIT_SIM_OBJECT_PARAMS(PciDev) 291 292CREATE_SIM_OBJECT(PciDev) 293{ 294 PciDev *dev = new PciDev(getInstanceName(), cf, bus, device, func); 295 296 dev->config.hdr.vendor = VendorID; 297 dev->config.hdr.device = DeviceID; 298 dev->config.hdr.command = Command; 299 dev->config.hdr.status = Status; 300 dev->config.hdr.revision = Revision; 301 dev->config.hdr.progIF = ProgIF; 302 dev->config.hdr.subClassCode = SubClassCode; 303 dev->config.hdr.classCode = ClassCode; 304 dev->config.hdr.cacheLineSize = CacheLineSize; 305 dev->config.hdr.latencyTimer = LatencyTimer; 306 dev->config.hdr.headerType = HeaderType; 307 dev->config.hdr.bist = BIST; 308 309 dev->config.hdr.pci0.baseAddr0 = BAR0; 310 dev->config.hdr.pci0.baseAddr1 = BAR1; 311 dev->config.hdr.pci0.baseAddr2 = BAR2; 312 dev->config.hdr.pci0.baseAddr3 = BAR3; 313 dev->config.hdr.pci0.baseAddr4 = BAR4; 314 dev->config.hdr.pci0.baseAddr5 = BAR5; 315 dev->config.hdr.pci0.cardbusCIS = CardbusCIS; 316 dev->config.hdr.pci0.subsystemVendorID = SubsystemVendorID; 317 dev->config.hdr.pci0.subsystemID = SubsystemVendorID; 318 dev->config.hdr.pci0.expansionROM = ExpansionROM; 319 dev->config.hdr.pci0.interruptLine = InterruptLine; 320 dev->config.hdr.pci0.interruptPin = InterruptPin; 321 dev->config.hdr.pci0.minimumGrant = MinimumGrant; 322 dev->config.hdr.pci0.maximumLatency = MaximumLatency; 323 324 dev->BARSize[0] = BAR0Size; 325 dev->BARSize[1] = BAR1Size; 326 dev->BARSize[2] = BAR2Size; 327 dev->BARSize[3] = BAR3Size; 328 dev->BARSize[4] = BAR4Size; 329 dev->BARSize[5] = BAR5Size; 330 331 return dev; 332} 333 334REGISTER_SIM_OBJECT("PciDev", PciDev) 335