device.cc revision 793
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/* @file 30 * A single PCI device configuration space entry. 31 */ 32 33#include <list> 34#include <sstream> 35#include <string> 36#include <vector> 37 38#include "base/inifile.hh" 39#include "base/misc.hh" 40#include "base/str.hh" // for to_number 41#include "base/trace.hh" 42#include "dev/pciareg.h" 43#include "dev/scsi_ctrl.hh" 44#include "dev/pcidev.hh" 45#include "dev/pciconfigall.hh" 46#include "mem/functional_mem/memory_control.hh" 47#include "sim/builder.hh" 48#include "sim/param.hh" 49#include "sim/universe.hh" 50 51using namespace std; 52 53PciDev::PciDev(const string &name, PCIConfigAll *cf, uint32_t bus, 54 uint32_t dev, uint32_t func) 55 : MMapDevice(name), ConfigSpace(cf), Bus(bus), Device(dev), Function(func) 56{ 57 memset(config.data, 0, sizeof(config.data)); 58 59 // Setup pointer in config space to point to this entry 60 if(cf->devices[dev][func] != NULL) 61 panic("Two PCI devices occuping same dev: %#x func: %#x", dev, func); 62 else 63 cf->devices[dev][func] = this; 64} 65 66 67void 68PciDev::ReadConfig(int offset, int size, uint8_t *data) 69{ 70 switch(size) { 71 case sizeof(uint32_t): 72 memcpy((uint32_t*)data, config.data + offset, sizeof(uint32_t)); 73 DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n", 74 Device, Function, offset, *(uint32_t*)(config.data + offset)); 75 break; 76 case sizeof(uint16_t): 77 memcpy((uint16_t*)data, config.data + offset, sizeof(uint16_t)); 78 DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n", 79 Device, Function, offset, *(uint16_t*)(config.data + offset)); 80 break; 81 case sizeof(uint8_t): 82 memcpy((uint8_t*)data, config.data + offset, sizeof(uint8_t)); 83 printf("data: %#x\n", *(uint8_t*)(config.data + offset)); 84 DPRINTF(PCIDEV, "read device: %#x function: %#x register: %#x data: %#x\n", 85 Device, Function, offset, *(uint8_t*)(config.data + offset)); 86 break; 87 default: 88 panic("Invalid Read Size"); 89 } 90} 91 92 93void 94PciDev::WriteConfig(int offset, int size, uint32_t data) 95{ 96 union { 97 uint8_t byte_value; 98 uint16_t half_value; 99 uint32_t word_value; 100 }; 101 word_value = data; 102 103 DPRINTF(PCIDEV, "write device: %#x function: %#x register: %#x size: %#x data: %#x\n", 104 Device, Function, offset, size, word_value); 105 106 switch (size) { 107 case sizeof(uint8_t): // 1-byte access 108 switch (offset) { 109 case PCI0_INTERRUPT_LINE: 110 case PCI_CACHE_LINE_SIZE: 111 *(uint8_t *)&config.data[offset] = byte_value; 112 break; 113 114 default: 115 panic("writing to a read only register"); 116 } 117 break; 118 119 case sizeof(uint16_t): // 2-byte access 120 switch (offset) { 121 case PCI_COMMAND: 122 case PCI_STATUS: 123 case PCI_CACHE_LINE_SIZE: 124 *(uint16_t *)&config.data[offset] = half_value; 125 break; 126 127 default: 128 panic("writing to a read only register"); 129 } 130 break; 131 132 case sizeof(uint16_t)+1: // 3-byte access 133 panic("invalid access size"); 134 135 case sizeof(uint32_t): // 4-byte access 136 switch (offset) { 137 case PCI0_BASE_ADDR0: 138 case PCI0_BASE_ADDR1: 139 case PCI0_BASE_ADDR2: 140 case PCI0_BASE_ADDR3: 141 case PCI0_BASE_ADDR4: 142 case PCI0_BASE_ADDR5: 143 // Writing 0xffffffff to a BAR tells the card to set the value of the bar 144 // to size of memory it needs 145 if (word_value == 0xffffffff) { 146 // This is I/O Space, bottom two bits are read only 147 if(config.data[offset] & 0x1) { 148 *(uint32_t *)&config.data[offset] = 149 ~(BARSize[offset-PCI0_BASE_ADDR0] - 1) | (config.data[offset] & 0x3); 150 } else { 151 // This is memory space, bottom four bits are read only 152 *(uint32_t *)&config.data[offset] = 153 ~(BARSize[(offset-PCI0_BASE_ADDR0)>>2] - 1) | (config.data[offset] & 0xF); 154 } 155 156 157 } else { 158 // This is I/O Space, bottom two bits are read only 159 if(config.data[offset] & 0x1) { 160 *(uint32_t *)&config.data[offset] = (word_value & ~0x3) | 161 (config.data[offset] & 0x3); 162 } else { 163 // This is memory space, bottom four bits are read only 164 *(uint32_t *)&config.data[offset] = (word_value & ~0xF) | 165 (config.data[offset] & 0xF); 166 } 167 } 168 break; 169 case PCI0_ROM_BASE_ADDR: 170 if (word_value == 0xfffffffe) 171 *(uint32_t *)&config.data[offset] = 0xffffffff; 172 else 173 *(uint32_t *)&config.data[offset] = word_value; 174 break; 175 case PCI_COMMAND: 176 // This could also clear some of the error bits in the Status register 177 // However they should never get set, so lets ignore it for now 178 *(uint16_t *)&config.data[offset] = half_value; 179 break; 180 181 182 default: 183 panic("writing to a read only register"); 184 } 185 break; 186 } 187 188} 189 190void 191PciDev::serialize(ostream &os) 192{ 193 SERIALIZE_ARRAY(config.data, 64); 194} 195 196void 197PciDev::unserialize(Checkpoint *cp, const std::string §ion) 198{ 199 UNSERIALIZE_ARRAY(config.data, 64); 200} 201 202 203BEGIN_DECLARE_SIM_OBJECT_PARAMS(PciDev) 204 205 Param<int> VendorID; 206 Param<int> DeviceID; 207 Param<int> Command; 208 Param<int> Status; 209 Param<int> Revision; 210 Param<int> ProgIF; 211 Param<int> SubClassCode; 212 Param<int> ClassCode; 213 Param<int> CacheLineSize; 214 Param<int> LatencyTimer; 215 Param<int> HeaderType; 216 Param<int> BIST; 217 Param<uint32_t> BAR0; 218 Param<uint32_t> BAR1; 219 Param<uint32_t> BAR2; 220 Param<uint32_t> BAR3; 221 Param<uint32_t> BAR4; 222 Param<uint32_t> BAR5; 223 Param<uint32_t> CardbusCIS; 224 Param<int> SubsystemVendorID; 225 Param<int> SubsystemID; 226 Param<uint32_t> ExpansionROM; 227 Param<int> InterruptLine; 228 Param<int> InterruptPin; 229 Param<int> MinimumGrant; 230 Param<int> MaximumLatency; 231 Param<uint32_t> BAR0Size; 232 Param<uint32_t> BAR1Size; 233 Param<uint32_t> BAR2Size; 234 Param<uint32_t> BAR3Size; 235 Param<uint32_t> BAR4Size; 236 Param<uint32_t> BAR5Size; 237 238 SimObjectParam<MemoryController *> mmu; 239 SimObjectParam<PCIConfigAll*> cf; 240 Param<Addr> addr; 241 Param<Addr> mask; 242 Param<uint32_t> bus; 243 Param<uint32_t> device; 244 Param<uint32_t> func; 245 246 247END_DECLARE_SIM_OBJECT_PARAMS(PciDev) 248 249BEGIN_INIT_SIM_OBJECT_PARAMS(PciDev) 250 251 INIT_PARAM(VendorID, "Vendor ID"), 252 INIT_PARAM(DeviceID, "Device ID"), 253 INIT_PARAM_DFLT(Command, "Command Register", 0x00), 254 INIT_PARAM_DFLT(Status, "Status Register", 0x00), 255 INIT_PARAM_DFLT(Revision, "Device Revision", 0x00), 256 INIT_PARAM_DFLT(ProgIF, "Programming Interface", 0x00), 257 INIT_PARAM(SubClassCode, "Sub-Class Code"), 258 INIT_PARAM(ClassCode, "Class Code"), 259 INIT_PARAM_DFLT(CacheLineSize, "System Cacheline Size", 0x00), 260 INIT_PARAM_DFLT(LatencyTimer, "PCI Latency Timer", 0x00), 261 INIT_PARAM_DFLT(HeaderType, "PCI Header Type", 0x00), 262 INIT_PARAM_DFLT(BIST, "Built In Self Test", 0x00), 263 INIT_PARAM_DFLT(BAR0, "Base Address Register 0", 0x00), 264 INIT_PARAM_DFLT(BAR1, "Base Address Register 1", 0x00), 265 INIT_PARAM_DFLT(BAR2, "Base Address Register 2", 0x00), 266 INIT_PARAM_DFLT(BAR3, "Base Address Register 3", 0x00), 267 INIT_PARAM_DFLT(BAR4, "Base Address Register 4", 0x00), 268 INIT_PARAM_DFLT(BAR5, "Base Address Register 5", 0x00), 269 INIT_PARAM_DFLT(CardbusCIS, "Cardbus Card Information Structure", 0x00), 270 INIT_PARAM_DFLT(SubsystemVendorID, "Subsystem Vendor ID", 0x00), 271 INIT_PARAM_DFLT(SubsystemID, "Subsystem ID", 0x00), 272 INIT_PARAM_DFLT(ExpansionROM, "Expansion ROM Base Address Register", 0x00), 273 INIT_PARAM(InterruptLine, "Interrupt Line Register"), 274 INIT_PARAM(InterruptPin, "Interrupt Pin Register"), 275 INIT_PARAM_DFLT(MinimumGrant, "Minimum Grant", 0x00), 276 INIT_PARAM_DFLT(MaximumLatency, "Maximum Latency", 0x00), 277 INIT_PARAM_DFLT(BAR0Size, "Base Address Register 0 Size", 0x00), 278 INIT_PARAM_DFLT(BAR1Size, "Base Address Register 1 Size", 0x00), 279 INIT_PARAM_DFLT(BAR2Size, "Base Address Register 2 Size", 0x00), 280 INIT_PARAM_DFLT(BAR3Size, "Base Address Register 3 Size", 0x00), 281 INIT_PARAM_DFLT(BAR4Size, "Base Address Register 4 Size", 0x00), 282 INIT_PARAM_DFLT(BAR5Size, "Base Address Register 5 Size", 0x00), 283 284 INIT_PARAM(cf, "Pointer to Configspace device"), 285 INIT_PARAM(bus, "PCI Bus Number"), 286 INIT_PARAM(device, "PCI Device number"), 287 INIT_PARAM(func, "PCI Function Number") 288 289 290END_INIT_SIM_OBJECT_PARAMS(PciDev) 291 292CREATE_SIM_OBJECT(PciDev) 293{ 294 PciDev *dev = new PciDev(getInstanceName(), cf, bus, device, func); 295 296 dev->config.hdr.vendor = VendorID; 297 dev->config.hdr.device = DeviceID; 298 dev->config.hdr.command = Command; 299 dev->config.hdr.status = Status; 300 dev->config.hdr.revision = Revision; 301 dev->config.hdr.progIF = ProgIF; 302 dev->config.hdr.subClassCode = SubClassCode; 303 dev->config.hdr.classCode = ClassCode; 304 dev->config.hdr.cacheLineSize = CacheLineSize; 305 dev->config.hdr.latencyTimer = LatencyTimer; 306 dev->config.hdr.headerType = HeaderType; 307 dev->config.hdr.bist = BIST; 308 309 dev->config.hdr.pci0.baseAddr0 = BAR0; 310 dev->config.hdr.pci0.baseAddr1 = BAR1; 311 dev->config.hdr.pci0.baseAddr2 = BAR2; 312 dev->config.hdr.pci0.baseAddr3 = BAR3; 313 dev->config.hdr.pci0.baseAddr4 = BAR4; 314 dev->config.hdr.pci0.baseAddr5 = BAR5; 315 dev->config.hdr.pci0.cardbusCIS = CardbusCIS; 316 dev->config.hdr.pci0.subsystemVendorID = SubsystemVendorID; 317 dev->config.hdr.pci0.subsystemID = SubsystemVendorID; 318 dev->config.hdr.pci0.expansionROM = ExpansionROM; 319 dev->config.hdr.pci0.interruptLine = InterruptLine; 320 dev->config.hdr.pci0.interruptPin = InterruptPin; 321 dev->config.hdr.pci0.minimumGrant = MinimumGrant; 322 dev->config.hdr.pci0.maximumLatency = MaximumLatency; 323 324 dev->BARSize[0] = BAR0Size; 325 dev->BARSize[1] = BAR1Size; 326 dev->BARSize[2] = BAR2Size; 327 dev->BARSize[3] = BAR3Size; 328 dev->BARSize[4] = BAR4Size; 329 dev->BARSize[5] = BAR5Size; 330 331 return dev; 332} 333 334REGISTER_SIM_OBJECT("PciDev", PciDev) 335