PciDevice.py revision 4982
12330SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 22330SN/A# All rights reserved. 32330SN/A# 42330SN/A# Redistribution and use in source and binary forms, with or without 52330SN/A# modification, are permitted provided that the following conditions are 62330SN/A# met: redistributions of source code must retain the above copyright 72330SN/A# notice, this list of conditions and the following disclaimer; 82330SN/A# redistributions in binary form must reproduce the above copyright 92330SN/A# notice, this list of conditions and the following disclaimer in the 102330SN/A# documentation and/or other materials provided with the distribution; 112330SN/A# neither the name of the copyright holders nor the names of its 122330SN/A# contributors may be used to endorse or promote products derived from 132330SN/A# this software without specific prior written permission. 142330SN/A# 152330SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162330SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172330SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182330SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192330SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202330SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212330SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222330SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232330SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242330SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252330SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262330SN/A# 272689Sktlim@umich.edu# Authors: Nathan Binkert 282689Sktlim@umich.edu 292330SN/Afrom m5.SimObject import SimObject 302292SN/Afrom m5.params import * 312292SN/Afrom m5.proxy import * 322292SN/Afrom Device import BasicPioDevice, DmaDevice, PioDevice 332292SN/A 342683Sktlim@umich.educlass PciConfigAll(PioDevice): 352680Sktlim@umich.edu type = 'PciConfigAll' 362292SN/A pio_latency = Param.Tick(1, "Programmed IO latency in simticks") 372678Sktlim@umich.edu bus = Param.UInt8(0x00, "PCI bus to act as config space for") 382683Sktlim@umich.edu size = Param.MemorySize32('16MB', "Size of config space") 392678Sktlim@umich.edu 402683Sktlim@umich.edu 412678Sktlim@umich.educlass PciDevice(DmaDevice): 422678Sktlim@umich.edu type = 'PciDevice' 432292SN/A abstract = True 442292SN/A config = Port(Self.pio.peerObj.port, "PCI configuration space port") 452292SN/A pci_bus = Param.Int("PCI bus") 462292SN/A pci_dev = Param.Int("PCI device number") 472330SN/A pci_func = Param.Int("PCI function code") 482330SN/A pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") 492330SN/A config_latency = Param.Latency('20ns', "Config read or write latency") 502292SN/A 512292SN/A VendorID = Param.UInt16("Vendor ID") 522330SN/A DeviceID = Param.UInt16("Device ID") 532330SN/A Command = Param.UInt16(0, "Command") 542330SN/A Status = Param.UInt16(0, "Status") 552330SN/A Revision = Param.UInt8(0, "Device") 562330SN/A ProgIF = Param.UInt8(0, "Programming Interface") 572330SN/A SubClassCode = Param.UInt8(0, "Sub-Class Code") 582292SN/A ClassCode = Param.UInt8(0, "Class Code") 592683Sktlim@umich.edu CacheLineSize = Param.UInt8(0, "System Cacheline Size") 602683Sktlim@umich.edu LatencyTimer = Param.UInt8(0, "PCI Latency Timer") 612292SN/A HeaderType = Param.UInt8(0, "PCI Header Type") 622683Sktlim@umich.edu BIST = Param.UInt8(0, "Built In Self Test") 632292SN/A 642791Sktlim@umich.edu BAR0 = Param.UInt32(0x00, "Base Address Register 0") 652791Sktlim@umich.edu BAR1 = Param.UInt32(0x00, "Base Address Register 1") 662292SN/A BAR2 = Param.UInt32(0x00, "Base Address Register 2") 672683Sktlim@umich.edu BAR3 = Param.UInt32(0x00, "Base Address Register 3") 682683Sktlim@umich.edu BAR4 = Param.UInt32(0x00, "Base Address Register 4") 692683Sktlim@umich.edu BAR5 = Param.UInt32(0x00, "Base Address Register 5") 702683Sktlim@umich.edu BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size") 712683Sktlim@umich.edu BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size") 722683Sktlim@umich.edu BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size") 732683Sktlim@umich.edu BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") 742683Sktlim@umich.edu BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") 752683Sktlim@umich.edu BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") 762683Sktlim@umich.edu 772683Sktlim@umich.edu CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") 782683Sktlim@umich.edu SubsystemID = Param.UInt16(0x00, "Subsystem ID") 792683Sktlim@umich.edu SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") 802683Sktlim@umich.edu ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") 812683Sktlim@umich.edu InterruptLine = Param.UInt8(0x00, "Interrupt Line") 822683Sktlim@umich.edu InterruptPin = Param.UInt8(0x00, "Interrupt Pin") 832683Sktlim@umich.edu MaximumLatency = Param.UInt8(0x00, "Maximum Latency") 842683Sktlim@umich.edu MinimumGrant = Param.UInt8(0x00, "Minimum Grant") 852683Sktlim@umich.edu 862683Sktlim@umich.edu 872683Sktlim@umich.edu