PciDevice.py revision 4486
19651SAndreas.Sandberg@ARM.com# Copyright (c) 2005-2007 The Regents of The University of Michigan 29651SAndreas.Sandberg@ARM.com# All rights reserved. 39651SAndreas.Sandberg@ARM.com# 49651SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 59651SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 69651SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 79651SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 89651SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 99651SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 109651SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 119651SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 129651SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 139651SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 149651SAndreas.Sandberg@ARM.com# 159651SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 169651SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 179651SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 189651SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 199651SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 209651SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 219651SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 229651SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 239651SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 249651SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 259651SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 269651SAndreas.Sandberg@ARM.com# 279651SAndreas.Sandberg@ARM.com# Authors: Nathan Binkert 289651SAndreas.Sandberg@ARM.com 299651SAndreas.Sandberg@ARM.comfrom m5.SimObject import SimObject 309651SAndreas.Sandberg@ARM.comfrom m5.params import * 319651SAndreas.Sandberg@ARM.comfrom m5.proxy import * 329651SAndreas.Sandberg@ARM.comfrom Device import BasicPioDevice, DmaDevice, PioDevice 339651SAndreas.Sandberg@ARM.com 349651SAndreas.Sandberg@ARM.comclass PciConfigData(SimObject): 359651SAndreas.Sandberg@ARM.com type = 'PciConfigData' 369651SAndreas.Sandberg@ARM.com VendorID = Param.UInt16("Vendor ID") 379651SAndreas.Sandberg@ARM.com DeviceID = Param.UInt16("Device ID") 389651SAndreas.Sandberg@ARM.com Command = Param.UInt16(0, "Command") 399651SAndreas.Sandberg@ARM.com Status = Param.UInt16(0, "Status") 409651SAndreas.Sandberg@ARM.com Revision = Param.UInt8(0, "Device") 419651SAndreas.Sandberg@ARM.com ProgIF = Param.UInt8(0, "Programming Interface") 429651SAndreas.Sandberg@ARM.com SubClassCode = Param.UInt8(0, "Sub-Class Code") 439651SAndreas.Sandberg@ARM.com ClassCode = Param.UInt8(0, "Class Code") 449651SAndreas.Sandberg@ARM.com CacheLineSize = Param.UInt8(0, "System Cacheline Size") 459651SAndreas.Sandberg@ARM.com LatencyTimer = Param.UInt8(0, "PCI Latency Timer") 469651SAndreas.Sandberg@ARM.com HeaderType = Param.UInt8(0, "PCI Header Type") 479651SAndreas.Sandberg@ARM.com BIST = Param.UInt8(0, "Built In Self Test") 489651SAndreas.Sandberg@ARM.com 499651SAndreas.Sandberg@ARM.com BAR0 = Param.UInt32(0x00, "Base Address Register 0") 509651SAndreas.Sandberg@ARM.com BAR1 = Param.UInt32(0x00, "Base Address Register 1") 519657Sandreas.sandberg@arm.com BAR2 = Param.UInt32(0x00, "Base Address Register 2") 529657Sandreas.sandberg@arm.com BAR3 = Param.UInt32(0x00, "Base Address Register 3") 539657Sandreas.sandberg@arm.com BAR4 = Param.UInt32(0x00, "Base Address Register 4") 549657Sandreas.sandberg@arm.com BAR5 = Param.UInt32(0x00, "Base Address Register 5") 559651SAndreas.Sandberg@ARM.com BAR0Size = Param.MemorySize32('0B', "Base Address Register 0 Size") 569651SAndreas.Sandberg@ARM.com BAR1Size = Param.MemorySize32('0B', "Base Address Register 1 Size") 579651SAndreas.Sandberg@ARM.com BAR2Size = Param.MemorySize32('0B', "Base Address Register 2 Size") 589651SAndreas.Sandberg@ARM.com BAR3Size = Param.MemorySize32('0B', "Base Address Register 3 Size") 599651SAndreas.Sandberg@ARM.com BAR4Size = Param.MemorySize32('0B', "Base Address Register 4 Size") 609651SAndreas.Sandberg@ARM.com BAR5Size = Param.MemorySize32('0B', "Base Address Register 5 Size") 619651SAndreas.Sandberg@ARM.com 629651SAndreas.Sandberg@ARM.com CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure") 639651SAndreas.Sandberg@ARM.com SubsystemID = Param.UInt16(0x00, "Subsystem ID") 649651SAndreas.Sandberg@ARM.com SubsystemVendorID = Param.UInt16(0x00, "Subsystem Vendor ID") 65 ExpansionROM = Param.UInt32(0x00, "Expansion ROM Base Address") 66 InterruptLine = Param.UInt8(0x00, "Interrupt Line") 67 InterruptPin = Param.UInt8(0x00, "Interrupt Pin") 68 MaximumLatency = Param.UInt8(0x00, "Maximum Latency") 69 MinimumGrant = Param.UInt8(0x00, "Minimum Grant") 70 71class PciConfigAll(PioDevice): 72 type = 'PciConfigAll' 73 pio_latency = Param.Tick(1, "Programmed IO latency in simticks") 74 bus = Param.UInt8(0x00, "PCI bus to act as config space for") 75 size = Param.MemorySize32('16MB', "Size of config space") 76 77 78class PciDevice(DmaDevice): 79 type = 'PciDevice' 80 abstract = True 81 config = Port(Self.pio.peerObj.port, "PCI configuration space port") 82 pci_bus = Param.Int("PCI bus") 83 pci_dev = Param.Int("PCI device number") 84 pci_func = Param.Int("PCI function code") 85 pio_latency = Param.Latency('1ns', "Programmed IO latency in simticks") 86 configdata = Param.PciConfigData(Parent.any, "PCI Config data") 87 config_latency = Param.Latency('20ns', "Config read or write latency") 88