sinicreg.hh revision 2126
18926Sandreas.hansson@arm.com/* 27586SAli.Saidi@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 37586SAli.Saidi@arm.com * All rights reserved. 47586SAli.Saidi@arm.com * 57586SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 67586SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 77586SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 87586SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 97586SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 107586SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 117586SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 127586SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 133970Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 143005Sstever@eecs.umich.edu * this software without specific prior written permission. 153005Sstever@eecs.umich.edu * 163005Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173005Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183005Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193005Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203005Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213005Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223005Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233005Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243005Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253005Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263005Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273005Sstever@eecs.umich.edu */ 283005Sstever@eecs.umich.edu 293005Sstever@eecs.umich.edu#ifndef __DEV_SINICREG_HH__ 303005Sstever@eecs.umich.edu#define __DEV_SINICREG_HH__ 313005Sstever@eecs.umich.edu 323005Sstever@eecs.umich.edu#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL) 333005Sstever@eecs.umich.edu#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL) 343005Sstever@eecs.umich.edu 353005Sstever@eecs.umich.edu#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \ 363005Sstever@eecs.umich.edu static const uint32_t NAME##_width = WIDTH; \ 373005Sstever@eecs.umich.edu static const uint32_t NAME##_offset = OFFSET; \ 383005Sstever@eecs.umich.edu static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \ 393005Sstever@eecs.umich.edu static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \ 403005Sstever@eecs.umich.edu static inline uint32_t get_##NAME(uint32_t reg) \ 416654Snate@binkert.org { return (reg & NAME) >> OFFSET; } \ 426654Snate@binkert.org static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \ 432889SN/A { return (reg & ~NAME) | ((val << OFFSET) & NAME); } 442710SN/A 456654Snate@binkert.org#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \ 466654Snate@binkert.org static const uint64_t NAME##_width = WIDTH; \ 476654Snate@binkert.org static const uint64_t NAME##_offset = OFFSET; \ 485457Ssaidi@eecs.umich.edu static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \ 496654Snate@binkert.org static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \ 506654Snate@binkert.org static inline uint64_t get_##NAME(uint64_t reg) \ 512934SN/A { return (reg & NAME) >> OFFSET; } \ 522549SN/A static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \ 532995SN/A { return (reg & ~NAME) | ((val << OFFSET) & NAME); } 543395Shsul@eecs.umich.edu 556981SLisa.Hsu@amd.comnamespace Sinic { 563448Shsul@eecs.umich.edunamespace Regs { 578920Snilay@cs.wisc.edu 583444Sktlim@umich.edustatic const int VirtualMask = 0xff; 592889SN/Astatic const int VirtualShift = 8; 608920Snilay@cs.wisc.edu 618920Snilay@cs.wisc.edu// Registers 623322Shsul@eecs.umich.edu__SINIC_REG32(Config, 0x00); // 32: configuration register 632710SN/A__SINIC_REG32(Command, 0x04); // 32: command register 642710SN/A__SINIC_REG32(IntrStatus, 0x08); // 32: interrupt status 652710SN/A__SINIC_REG32(IntrMask, 0x0c); // 32: interrupt mask 662710SN/A__SINIC_REG32(RxMaxCopy, 0x10); // 32: max bytes per rx copy 672710SN/A__SINIC_REG32(TxMaxCopy, 0x14); // 32: max bytes per tx copy 682710SN/A__SINIC_REG32(RxMaxIntr, 0x18); // 32: max receives per interrupt 693322Shsul@eecs.umich.edu__SINIC_REG32(Reserved0, 0x1c); // 32: reserved 703304Sstever@eecs.umich.edu__SINIC_REG32(RxFifoSize, 0x20); // 32: rx fifo capacity in bytes 713322Shsul@eecs.umich.edu__SINIC_REG32(TxFifoSize, 0x24); // 32: tx fifo capacity in bytes 723322Shsul@eecs.umich.edu__SINIC_REG32(RxFifoMark, 0x28); // 32: rx fifo high watermark 733304Sstever@eecs.umich.edu__SINIC_REG32(TxFifoMark, 0x2c); // 32: tx fifo low watermark 743481Shsul@eecs.umich.edu__SINIC_REG32(RxData, 0x30); // 64: receive data 753481Shsul@eecs.umich.edu__SINIC_REG32(RxDone, 0x38); // 64: receive done 762566SN/A__SINIC_REG32(RxWait, 0x40); // 64: receive done (busy wait) 779129Sandreas.hansson@arm.com__SINIC_REG32(TxData, 0x48); // 64: transmit data 789129Sandreas.hansson@arm.com__SINIC_REG32(TxDone, 0x50); // 64: transmit done 792995SN/A__SINIC_REG32(TxWait, 0x58); // 64: transmit done (busy wait) 802995SN/A__SINIC_REG32(HwAddr, 0x60); // 64: mac address 813304Sstever@eecs.umich.edu__SINIC_REG32(Size, 0x68); // register addres space size 823304Sstever@eecs.umich.edu 833304Sstever@eecs.umich.edu// Config register bits 842995SN/A__SINIC_VAL32(Config_RxThread, 9, 1); // enable receive threads 852995SN/A__SINIC_VAL32(Config_TxThread, 8, 1); // enable transmit thread 862995SN/A__SINIC_VAL32(Config_Filter, 7, 1); // enable receive filter 872917SN/A__SINIC_VAL32(Config_Vlan, 6, 1); // enable vlan tagging 882995SN/A__SINIC_VAL32(Config_Virtual, 5, 1); // enable virtual addressing 898956Sjayneel@cs.wisc.edu__SINIC_VAL32(Config_Desc, 4, 1); // enable tx/rx descriptors 902995SN/A__SINIC_VAL32(Config_Poll, 3, 1); // enable polling 918956Sjayneel@cs.wisc.edu__SINIC_VAL32(Config_IntEn, 2, 1); // enable interrupts 923304Sstever@eecs.umich.edu__SINIC_VAL32(Config_TxEn, 1, 1); // enable transmit 936135Sgblack@eecs.umich.edu__SINIC_VAL32(Config_RxEn, 0, 1); // enable receive 946135Sgblack@eecs.umich.edu 956654Snate@binkert.org// Command register bits 963819Shsul@eecs.umich.edu__SINIC_VAL32(Command_Intr, 1, 1); // software interrupt 976654Snate@binkert.org__SINIC_VAL32(Command_Reset, 0, 1); // reset chip 985222Sksewell@umich.edu 996654Snate@binkert.org// Interrupt register bits 1003819Shsul@eecs.umich.edu__SINIC_VAL32(Intr_Soft, 8, 1); // software interrupt 1016654Snate@binkert.org__SINIC_VAL32(Intr_TxLow, 7, 1); // tx fifo dropped below watermark 1027925Sgblack@eecs.umich.edu__SINIC_VAL32(Intr_TxFull, 6, 1); // tx fifo full 1037586SAli.Saidi@arm.com__SINIC_VAL32(Intr_TxDMA, 5, 1); // tx dma completed w/ interrupt 1049539Satgutier@umich.edu__SINIC_VAL32(Intr_TxPacket, 4, 1); // packet transmitted 1059539Satgutier@umich.edu__SINIC_VAL32(Intr_RxHigh, 3, 1); // rx fifo above high watermark 1063819Shsul@eecs.umich.edu__SINIC_VAL32(Intr_RxEmpty, 2, 1); // rx fifo empty 1079059Snilay@cs.wisc.edu__SINIC_VAL32(Intr_RxDMA, 1, 1); // rx dma completed w/ interrupt 1083819Shsul@eecs.umich.edu__SINIC_VAL32(Intr_RxPacket, 0, 1); // packet received 1093873Sbinkertn@umich.edu__SINIC_REG32(Intr_All, 0x01ff); // all valid interrupts 1103873Sbinkertn@umich.edu__SINIC_REG32(Intr_NoDelay, 0x01cc); // interrupts that aren't coalesced 1113873Sbinkertn@umich.edu__SINIC_REG32(Intr_Res, ~0x01ff); // reserved interrupt bits 1123873Sbinkertn@umich.edu 1133873Sbinkertn@umich.edu// RX Data Description 1143873Sbinkertn@umich.edu__SINIC_VAL64(RxData_Len, 40, 20); // 0 - 1M 1158659SAli.Saidi@ARM.com__SINIC_VAL64(RxData_Addr, 0, 40); // Address 1TB 1168659SAli.Saidi@ARM.com 1176995Sgblack@eecs.umich.edu// TX Data Description 1183668Srdreslin@umich.edu__SINIC_VAL64(TxData_More, 63, 1); // Packet not complete (will dma more) 1196636Ssteve.reinhardt@amd.com__SINIC_VAL64(TxData_Checksum, 62, 1); // do checksum 1209288Sandreas.hansson@arm.com__SINIC_VAL64(TxData_Len, 40, 20); // 0 - 1M 1219408Sandreas.hansson@arm.com__SINIC_VAL64(TxData_Addr, 0, 40); // Address 1TB 1228839Sandreas.hansson@arm.com 1238839Sandreas.hansson@arm.com// RX Done/Busy Information 1248713Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_Packets, 32, 16); // number of packets in rx fifo 1259408Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_Busy, 31, 1); // receive dma busy copying 1268839Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_Complete, 30, 1); // valid data (packet complete) 1278839Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_More, 29, 1); // Packet has more data (dma again) 1285142Ssaidi@eecs.umich.edu__SINIC_VAL64(RxDone_Res0, 28, 1); // reserved 1298926Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_Res1, 27, 1); // reserved 1309317Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_Res2, 26, 1); // reserved 1319317Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_TcpError, 25, 1); // TCP packet error (bad checksum) 1329317Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_UdpError, 24, 1); // UDP packet error (bad checksum) 1339317Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_IpError, 23, 1); // IP packet error (bad checksum) 1349317Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_TcpPacket, 22, 1); // this is a TCP packet 1358926Sandreas.hansson@arm.com__SINIC_VAL64(RxDone_UdpPacket, 21, 1); // this is a UDP packet 1363312Sstever@eecs.umich.edu__SINIC_VAL64(RxDone_IpPacket, 20, 1); // this is an IP packet 1374968Sacolyte@umich.edu__SINIC_VAL64(RxDone_CopyLen, 0, 20); // up to 256k 1388926Sandreas.hansson@arm.com 1398887Sgeoffrey.blake@arm.com// TX Done/Busy Information 1408887Sgeoffrey.blake@arm.com__SINIC_VAL64(TxDone_Packets, 32, 16); // number of packets in tx fifo 1419384SAndreas.Sandberg@arm.com__SINIC_VAL64(TxDone_Busy, 31, 1); // transmit dma busy copying 1428887Sgeoffrey.blake@arm.com__SINIC_VAL64(TxDone_Complete, 30, 1); // valid data (packet complete) 1438887Sgeoffrey.blake@arm.com__SINIC_VAL64(TxDone_Full, 29, 1); // tx fifo is full 1444968Sacolyte@umich.edu__SINIC_VAL64(TxDone_Low, 28, 1); // tx fifo is below the watermark 1453005Sstever@eecs.umich.edu__SINIC_VAL64(TxDone_Res0, 27, 1); // reserved 1466654Snate@binkert.org__SINIC_VAL64(TxDone_Res1, 26, 1); // reserved 1473819Shsul@eecs.umich.edu__SINIC_VAL64(TxDone_Res2, 25, 1); // reserved 1486654Snate@binkert.org__SINIC_VAL64(TxDone_Res3, 24, 1); // reserved 1495222Sksewell@umich.edu__SINIC_VAL64(TxDone_Res4, 23, 1); // reserved 1506654Snate@binkert.org__SINIC_VAL64(TxDone_Res5, 22, 1); // reserved 1513819Shsul@eecs.umich.edu__SINIC_VAL64(TxDone_Res6, 21, 1); // reserved 1526654Snate@binkert.org__SINIC_VAL64(TxDone_Res7, 20, 1); // reserved 1536135Sgblack@eecs.umich.edu__SINIC_VAL64(TxDone_CopyLen, 0, 20); // up to 256k 1547586SAli.Saidi@arm.com 1558661SAli.Saidi@ARM.comstruct Info 1568661SAli.Saidi@ARM.com{ 1573322Shsul@eecs.umich.edu uint8_t size; 1589384SAndreas.Sandberg@arm.com bool read; 1598863Snilay@cs.wisc.edu bool write; 1607876Sgblack@eecs.umich.edu const char *name; 1614968Sacolyte@umich.edu}; 1628926Sandreas.hansson@arm.com 1634837Ssaidi@eecs.umich.edu/* namespace Regs */ } 1644837Ssaidi@eecs.umich.edu 1659408Sandreas.hansson@arm.cominline const Regs::Info& 1669164Sandreas.hansson@arm.comregInfo(TheISA::Addr daddr) 1679408Sandreas.hansson@arm.com{ 1688845Sandreas.hansson@arm.com static Regs::Info invalid = { 0, false, false, "invalid" }; 1698845Sandreas.hansson@arm.com static Regs::Info info [] = { 1704837Ssaidi@eecs.umich.edu { 4, true, true, "Config" }, 1718659SAli.Saidi@ARM.com { 4, false, true, "Command" }, 1728801Sgblack@eecs.umich.edu { 4, true, true, "IntrStatus" }, 1733005Sstever@eecs.umich.edu { 4, true, true, "IntrMask" }, 1748801Sgblack@eecs.umich.edu { 4, true, false, "RxMaxCopy" }, 1753005Sstever@eecs.umich.edu { 4, true, false, "TxMaxCopy" }, 1763005Sstever@eecs.umich.edu { 4, true, false, "RxMaxIntr" }, 1773005Sstever@eecs.umich.edu invalid, 1782566SN/A { 4, true, false, "RxFifoSize" }, 1797861Sgblack@eecs.umich.edu { 4, true, false, "TxFifoSize" }, 1807861Sgblack@eecs.umich.edu { 4, true, false, "RxFifoMark" }, 1817861Sgblack@eecs.umich.edu { 4, true, false, "TxFifoMark" }, 1828635Schris.emmons@arm.com { 8, true, true, "RxData" }, 1838635Schris.emmons@arm.com invalid, 1848635Schris.emmons@arm.com { 8, true, false, "RxDone" }, 1859061Snilay@cs.wisc.edu invalid, 1863481Shsul@eecs.umich.edu { 8, true, false, "RxWait" }, 187 invalid, 188 { 8, true, true, "TxData" }, 189 invalid, 190 { 8, true, false, "TxDone" }, 191 invalid, 192 { 8, true, false, "TxWait" }, 193 invalid, 194 { 8, true, false, "HwAddr" }, 195 invalid, 196 }; 197 198 return info[daddr / 4]; 199} 200 201inline bool 202regValid(TheISA::Addr daddr) 203{ 204 if (daddr > Regs::Size) 205 return false; 206 207 if (regInfo(daddr).size == 0) 208 return false; 209 210 return true; 211} 212 213/* namespace Sinic */ } 214 215#endif // __DEV_SINICREG_HH__ 216