sinicreg.hh revision 2665 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#ifndef __DEV_SINICREG_HH__
32#define __DEV_SINICREG_HH__
33
34#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL)
35#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL)
36
37#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
38        static const uint32_t NAME##_width = WIDTH; \
39        static const uint32_t NAME##_offset = OFFSET; \
40        static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
41        static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
42        static inline uint32_t get_##NAME(uint32_t reg) \
43        { return (reg & NAME) >> OFFSET; } \
44        static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
45        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
46
47#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
48        static const uint64_t NAME##_width = WIDTH; \
49        static const uint64_t NAME##_offset = OFFSET; \
50        static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
51        static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET;	\
52        static inline uint64_t get_##NAME(uint64_t reg) \
53        { return (reg & NAME) >> OFFSET; } \
54        static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
55        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
56
57namespace Sinic {
58namespace Regs {
59
60static const int VirtualShift = 8;
61static const int VirtualMask = 0xff;
62
63// Registers
64__SINIC_REG32(Config,        0x00); // 32: configuration register
65__SINIC_REG32(Command,       0x04); // 32: command register
66__SINIC_REG32(IntrStatus,    0x08); // 32: interrupt status
67__SINIC_REG32(IntrMask,      0x0c); // 32: interrupt mask
68__SINIC_REG32(RxMaxCopy,     0x10); // 32: max bytes per rx copy
69__SINIC_REG32(TxMaxCopy,     0x14); // 32: max bytes per tx copy
70__SINIC_REG32(RxMaxIntr,     0x18); // 32: max receives per interrupt
71__SINIC_REG32(VirtualCount,  0x1c); // 32: number of virutal NICs
72__SINIC_REG32(RxFifoSize,    0x20); // 32: rx fifo capacity in bytes
73__SINIC_REG32(TxFifoSize,    0x24); // 32: tx fifo capacity in bytes
74__SINIC_REG32(RxFifoMark,    0x28); // 32: rx fifo high watermark
75__SINIC_REG32(TxFifoMark,    0x2c); // 32: tx fifo low watermark
76__SINIC_REG32(RxData,        0x30); // 64: receive data
77__SINIC_REG32(RxDone,        0x38); // 64: receive done
78__SINIC_REG32(RxWait,        0x40); // 64: receive done (busy wait)
79__SINIC_REG32(TxData,        0x48); // 64: transmit data
80__SINIC_REG32(TxDone,        0x50); // 64: transmit done
81__SINIC_REG32(TxWait,        0x58); // 64: transmit done (busy wait)
82__SINIC_REG32(HwAddr,        0x60); // 64: mac address
83__SINIC_REG32(Size,          0x68); // register addres space size
84
85// Config register bits
86__SINIC_VAL32(Config_ZeroCopy, 12, 1); // enable zero copy
87__SINIC_VAL32(Config_DelayCopy,11, 1); // enable delayed copy
88__SINIC_VAL32(Config_RSS,      10, 1); // enable receive side scaling
89__SINIC_VAL32(Config_RxThread,  9, 1); // enable receive threads
90__SINIC_VAL32(Config_TxThread,  8, 1); // enable transmit thread
91__SINIC_VAL32(Config_Filter,    7, 1); // enable receive filter
92__SINIC_VAL32(Config_Vlan,      6, 1); // enable vlan tagging
93__SINIC_VAL32(Config_Vaddr,     5, 1); // enable virtual addressing
94__SINIC_VAL32(Config_Desc,      4, 1); // enable tx/rx descriptors
95__SINIC_VAL32(Config_Poll,      3, 1); // enable polling
96__SINIC_VAL32(Config_IntEn,     2, 1); // enable interrupts
97__SINIC_VAL32(Config_TxEn,      1, 1); // enable transmit
98__SINIC_VAL32(Config_RxEn,      0, 1); // enable receive
99
100// Command register bits
101__SINIC_VAL32(Command_Intr,  1, 1); // software interrupt
102__SINIC_VAL32(Command_Reset, 0, 1); // reset chip
103
104// Interrupt register bits
105__SINIC_VAL32(Intr_Soft,      8, 1); // software interrupt
106__SINIC_VAL32(Intr_TxLow,     7, 1); // tx fifo dropped below watermark
107__SINIC_VAL32(Intr_TxFull,    6, 1); // tx fifo full
108__SINIC_VAL32(Intr_TxDMA,     5, 1); // tx dma completed w/ interrupt
109__SINIC_VAL32(Intr_TxPacket,  4, 1); // packet transmitted
110__SINIC_VAL32(Intr_RxHigh,    3, 1); // rx fifo above high watermark
111__SINIC_VAL32(Intr_RxEmpty,   2, 1); // rx fifo empty
112__SINIC_VAL32(Intr_RxDMA,     1, 1); // rx dma completed w/ interrupt
113__SINIC_VAL32(Intr_RxPacket,  0, 1); // packet received
114__SINIC_REG32(Intr_All,       0x01ff); // all valid interrupts
115__SINIC_REG32(Intr_NoDelay,   0x01cc); // interrupts that aren't coalesced
116__SINIC_REG32(Intr_Res,      ~0x01ff); // reserved interrupt bits
117
118// RX Data Description
119__SINIC_VAL64(RxData_Vaddr, 60,  1); // Addr is virtual
120__SINIC_VAL64(RxData_Len,   40, 20); // 0 - 256k
121__SINIC_VAL64(RxData_Addr,   0, 40); // Address 1TB
122
123// TX Data Description
124__SINIC_VAL64(TxData_More,     63,  1); // Packet not complete (will dma more)
125__SINIC_VAL64(TxData_Checksum, 62,  1); // do checksum
126__SINIC_VAL64(TxData_Vaddr,    60,  1); // Addr is virtual
127__SINIC_VAL64(TxData_Len,      40, 20); // 0 - 256k
128__SINIC_VAL64(TxData_Addr,      0, 40); // Address 1TB
129
130// RX Done/Busy Information
131__SINIC_VAL64(RxDone_Packets,   32, 16); // number of packets in rx fifo
132__SINIC_VAL64(RxDone_Busy,      31,  1); // receive dma busy copying
133__SINIC_VAL64(RxDone_Complete,  30,  1); // valid data (packet complete)
134__SINIC_VAL64(RxDone_More,      29,  1); // Packet has more data (dma again)
135__SINIC_VAL64(RxDone_Empty,     28,  1); // rx fifo is empty
136__SINIC_VAL64(RxDone_High,      27,  1); // rx fifo is above the watermark
137__SINIC_VAL64(RxDone_NotHigh,   26,  1); // rxfifo never hit the high watermark
138__SINIC_VAL64(RxDone_TcpError,  25,  1); // TCP packet error (bad checksum)
139__SINIC_VAL64(RxDone_UdpError,  24,  1); // UDP packet error (bad checksum)
140__SINIC_VAL64(RxDone_IpError,   23,  1); // IP packet error (bad checksum)
141__SINIC_VAL64(RxDone_TcpPacket, 22,  1); // this is a TCP packet
142__SINIC_VAL64(RxDone_UdpPacket, 21,  1); // this is a UDP packet
143__SINIC_VAL64(RxDone_IpPacket,  20,  1); // this is an IP packet
144__SINIC_VAL64(RxDone_CopyLen,    0, 20); // up to 256k
145
146// TX Done/Busy Information
147__SINIC_VAL64(TxDone_Packets,   32, 16); // number of packets in tx fifo
148__SINIC_VAL64(TxDone_Busy,      31,  1); // transmit dma busy copying
149__SINIC_VAL64(TxDone_Complete,  30,  1); // valid data (packet complete)
150__SINIC_VAL64(TxDone_Full,      29,  1); // tx fifo is full
151__SINIC_VAL64(TxDone_Low,       28,  1); // tx fifo is below the watermark
152__SINIC_VAL64(TxDone_Res0,      27,  1); // reserved
153__SINIC_VAL64(TxDone_Res1,      26,  1); // reserved
154__SINIC_VAL64(TxDone_Res2,      25,  1); // reserved
155__SINIC_VAL64(TxDone_Res3,      24,  1); // reserved
156__SINIC_VAL64(TxDone_Res4,      23,  1); // reserved
157__SINIC_VAL64(TxDone_Res5,      22,  1); // reserved
158__SINIC_VAL64(TxDone_Res6,      21,  1); // reserved
159__SINIC_VAL64(TxDone_Res7,      20,  1); // reserved
160__SINIC_VAL64(TxDone_CopyLen,    0, 20); // up to 256k
161
162struct Info
163{
164    uint8_t size;
165    bool read;
166    bool write;
167    const char *name;
168};
169
170/* namespace Regs */ }
171
172inline const Regs::Info&
173regInfo(Addr daddr)
174{
175    static Regs::Info invalid = { 0, false, false, "invalid" };
176    static Regs::Info info [] = {
177        { 4, true,  true,  "Config"     },
178        { 4, false, true,  "Command"    },
179        { 4, true,  true,  "IntrStatus" },
180        { 4, true,  true,  "IntrMask"   },
181        { 4, true,  false, "RxMaxCopy"  },
182        { 4, true,  false, "TxMaxCopy"  },
183        { 4, true,  false, "RxMaxIntr"  },
184        { 4, true,  false, "VirtualCount"  },
185        { 4, true,  false, "RxFifoSize" },
186        { 4, true,  false, "TxFifoSize" },
187        { 4, true,  false, "RxFifoMark" },
188        { 4, true,  false, "TxFifoMark" },
189        { 8, true,  true,  "RxData"     },
190        invalid,
191        { 8, true,  false, "RxDone"     },
192        invalid,
193        { 8, true,  false, "RxWait"     },
194        invalid,
195        { 8, true,  true,  "TxData"     },
196        invalid,
197        { 8, true,  false, "TxDone"     },
198        invalid,
199        { 8, true,  false, "TxWait"     },
200        invalid,
201        { 8, true,  false, "HwAddr"     },
202        invalid,
203    };
204
205    return info[daddr / 4];
206}
207
208inline bool
209regValid(Addr daddr)
210{
211    if (daddr > Regs::Size)
212        return false;
213
214    if (regInfo(daddr).size == 0)
215        return false;
216
217    return true;
218}
219
220/* namespace Sinic */ }
221
222#endif // __DEV_SINICREG_HH__
223