sinicreg.hh revision 2130 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __DEV_SINICREG_HH__
30#define __DEV_SINICREG_HH__
31
32#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL)
33#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL)
34
35#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
36        static const uint32_t NAME##_width = WIDTH; \
37        static const uint32_t NAME##_offset = OFFSET; \
38        static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
39        static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
40        static inline uint32_t get_##NAME(uint32_t reg) \
41        { return (reg & NAME) >> OFFSET; } \
42        static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
43        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
44
45#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
46        static const uint64_t NAME##_width = WIDTH; \
47        static const uint64_t NAME##_offset = OFFSET; \
48        static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
49        static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET;	\
50        static inline uint64_t get_##NAME(uint64_t reg) \
51        { return (reg & NAME) >> OFFSET; } \
52        static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
53        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
54
55namespace Sinic {
56namespace Regs {
57
58static const int VirtualMask = 0xff;
59static const int VirtualShift = 8;
60
61// Registers
62__SINIC_REG32(Config,      0x00); // 32: configuration register
63__SINIC_REG32(Command,     0x04); // 32: command register
64__SINIC_REG32(IntrStatus,  0x08); // 32: interrupt status
65__SINIC_REG32(IntrMask,    0x0c); // 32: interrupt mask
66__SINIC_REG32(RxMaxCopy,   0x10); // 32: max bytes per rx copy
67__SINIC_REG32(TxMaxCopy,   0x14); // 32: max bytes per tx copy
68__SINIC_REG32(RxMaxIntr,   0x18); // 32: max receives per interrupt
69__SINIC_REG32(Reserved0,   0x1c); // 32: reserved
70__SINIC_REG32(RxFifoSize,  0x20); // 32: rx fifo capacity in bytes
71__SINIC_REG32(TxFifoSize,  0x24); // 32: tx fifo capacity in bytes
72__SINIC_REG32(RxFifoMark,  0x28); // 32: rx fifo high watermark
73__SINIC_REG32(TxFifoMark,  0x2c); // 32: tx fifo low watermark
74__SINIC_REG32(RxData,      0x30); // 64: receive data
75__SINIC_REG32(RxDone,      0x38); // 64: receive done
76__SINIC_REG32(RxWait,      0x40); // 64: receive done (busy wait)
77__SINIC_REG32(TxData,      0x48); // 64: transmit data
78__SINIC_REG32(TxDone,      0x50); // 64: transmit done
79__SINIC_REG32(TxWait,      0x58); // 64: transmit done (busy wait)
80__SINIC_REG32(HwAddr,      0x60); // 64: mac address
81__SINIC_REG32(Size,        0x68); // register addres space size
82
83// Config register bits
84__SINIC_VAL32(Config_RxThread,  9, 1); // enable receive threads
85__SINIC_VAL32(Config_TxThread,  8, 1); // enable transmit thread
86__SINIC_VAL32(Config_Filter,    7, 1); // enable receive filter
87__SINIC_VAL32(Config_Vlan,      6, 1); // enable vlan tagging
88__SINIC_VAL32(Config_Virtual,   5, 1); // enable virtual addressing
89__SINIC_VAL32(Config_Desc,      4, 1); // enable tx/rx descriptors
90__SINIC_VAL32(Config_Poll,      3, 1); // enable polling
91__SINIC_VAL32(Config_IntEn,     2, 1); // enable interrupts
92__SINIC_VAL32(Config_TxEn,      1, 1); // enable transmit
93__SINIC_VAL32(Config_RxEn,      0, 1); // enable receive
94
95// Command register bits
96__SINIC_VAL32(Command_Intr,  1, 1); // software interrupt
97__SINIC_VAL32(Command_Reset, 0, 1); // reset chip
98
99// Interrupt register bits
100__SINIC_VAL32(Intr_Soft,      8, 1); // software interrupt
101__SINIC_VAL32(Intr_TxLow,     7, 1); // tx fifo dropped below watermark
102__SINIC_VAL32(Intr_TxFull,    6, 1); // tx fifo full
103__SINIC_VAL32(Intr_TxDMA,     5, 1); // tx dma completed w/ interrupt
104__SINIC_VAL32(Intr_TxPacket,  4, 1); // packet transmitted
105__SINIC_VAL32(Intr_RxHigh,    3, 1); // rx fifo above high watermark
106__SINIC_VAL32(Intr_RxEmpty,   2, 1); // rx fifo empty
107__SINIC_VAL32(Intr_RxDMA,     1, 1); // rx dma completed w/ interrupt
108__SINIC_VAL32(Intr_RxPacket,  0, 1); // packet received
109__SINIC_REG32(Intr_All,       0x01ff); // all valid interrupts
110__SINIC_REG32(Intr_NoDelay,   0x01cc); // interrupts that aren't coalesced
111__SINIC_REG32(Intr_Res,      ~0x01ff); // reserved interrupt bits
112
113// RX Data Description
114__SINIC_VAL64(RxData_Len, 40, 20); // 0 - 1M
115__SINIC_VAL64(RxData_Addr, 0, 40); // Address 1TB
116
117// TX Data Description
118__SINIC_VAL64(TxData_More,     63,  1); // Packet not complete (will dma more)
119__SINIC_VAL64(TxData_Checksum, 62,  1); // do checksum
120__SINIC_VAL64(TxData_Len,      40, 20); // 0 - 1M
121__SINIC_VAL64(TxData_Addr,      0, 40); // Address 1TB
122
123// RX Done/Busy Information
124__SINIC_VAL64(RxDone_Packets,   32, 16); // number of packets in rx fifo
125__SINIC_VAL64(RxDone_Busy,      31,  1); // receive dma busy copying
126__SINIC_VAL64(RxDone_Complete,  30,  1); // valid data (packet complete)
127__SINIC_VAL64(RxDone_More,      29,  1); // Packet has more data (dma again)
128__SINIC_VAL64(RxDone_Res0,      28,  1); // reserved
129__SINIC_VAL64(RxDone_Res1,      27,  1); // reserved
130__SINIC_VAL64(RxDone_Res2,      26,  1); // reserved
131__SINIC_VAL64(RxDone_TcpError,  25,  1); // TCP packet error (bad checksum)
132__SINIC_VAL64(RxDone_UdpError,  24,  1); // UDP packet error (bad checksum)
133__SINIC_VAL64(RxDone_IpError,   23,  1); // IP packet error (bad checksum)
134__SINIC_VAL64(RxDone_TcpPacket, 22,  1); // this is a TCP packet
135__SINIC_VAL64(RxDone_UdpPacket, 21,  1); // this is a UDP packet
136__SINIC_VAL64(RxDone_IpPacket,  20,  1); // this is an IP packet
137__SINIC_VAL64(RxDone_CopyLen,    0, 20); // up to 256k
138
139// TX Done/Busy Information
140__SINIC_VAL64(TxDone_Packets,   32, 16); // number of packets in tx fifo
141__SINIC_VAL64(TxDone_Busy,      31,  1); // transmit dma busy copying
142__SINIC_VAL64(TxDone_Complete,  30,  1); // valid data (packet complete)
143__SINIC_VAL64(TxDone_Full,      29,  1); // tx fifo is full
144__SINIC_VAL64(TxDone_Low,       28,  1); // tx fifo is below the watermark
145__SINIC_VAL64(TxDone_Res0,      27,  1); // reserved
146__SINIC_VAL64(TxDone_Res1,      26,  1); // reserved
147__SINIC_VAL64(TxDone_Res2,      25,  1); // reserved
148__SINIC_VAL64(TxDone_Res3,      24,  1); // reserved
149__SINIC_VAL64(TxDone_Res4,      23,  1); // reserved
150__SINIC_VAL64(TxDone_Res5,      22,  1); // reserved
151__SINIC_VAL64(TxDone_Res6,      21,  1); // reserved
152__SINIC_VAL64(TxDone_Res7,      20,  1); // reserved
153__SINIC_VAL64(TxDone_CopyLen,    0, 20); // up to 256k
154
155struct Info
156{
157    uint8_t size;
158    bool read;
159    bool write;
160    const char *name;
161};
162
163/* namespace Regs */ }
164
165inline const Regs::Info&
166regInfo(Addr daddr)
167{
168    static Regs::Info invalid = { 0, false, false, "invalid" };
169    static Regs::Info info [] = {
170        { 4, true,  true,  "Config"     },
171        { 4, false, true,  "Command"    },
172        { 4, true,  true,  "IntrStatus" },
173        { 4, true,  true,  "IntrMask"   },
174        { 4, true,  false, "RxMaxCopy"  },
175        { 4, true,  false, "TxMaxCopy"  },
176        { 4, true,  false, "RxMaxIntr"  },
177        invalid,
178        { 4, true,  false, "RxFifoSize" },
179        { 4, true,  false, "TxFifoSize" },
180        { 4, true,  false, "RxFifoMark" },
181        { 4, true,  false, "TxFifoMark" },
182        { 8, true,  true,  "RxData"     },
183        invalid,
184        { 8, true,  false, "RxDone"     },
185        invalid,
186        { 8, true,  false, "RxWait"     },
187        invalid,
188        { 8, true,  true,  "TxData"     },
189        invalid,
190        { 8, true,  false, "TxDone"     },
191        invalid,
192        { 8, true,  false, "TxWait"     },
193        invalid,
194        { 8, true,  false, "HwAddr"     },
195        invalid,
196    };
197
198    return info[daddr / 4];
199}
200
201inline bool
202regValid(Addr daddr)
203{
204    if (daddr > Regs::Size)
205        return false;
206
207    if (regInfo(daddr).size == 0)
208        return false;
209
210    return true;
211}
212
213/* namespace Sinic */ }
214
215#endif // __DEV_SINICREG_HH__
216