sinicreg.hh revision 1997 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __DEV_SINICREG_HH__
30#define __DEV_SINICREG_HH__
31
32#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL)
33#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL)
34
35#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \
36        static const uint32_t NAME##_width = WIDTH; \
37        static const uint32_t NAME##_offset = OFFSET; \
38        static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \
39        static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \
40        static inline uint32_t get_##NAME(uint32_t reg) \
41        { return (reg & NAME) >> OFFSET; } \
42        static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \
43        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
44
45#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \
46        static const uint64_t NAME##_width = WIDTH; \
47        static const uint64_t NAME##_offset = OFFSET; \
48        static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \
49        static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET;	\
50        static inline uint64_t get_##NAME(uint64_t reg) \
51        { return (reg & NAME) >> OFFSET; } \
52        static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \
53        { return (reg & ~NAME) | ((val << OFFSET) & NAME); }
54
55namespace Sinic {
56namespace Regs {
57
58// Registers
59__SINIC_REG32(Config,      0x00); // 32: configuration register
60__SINIC_REG32(Command,     0x04); // 32: command register
61__SINIC_REG32(IntrStatus,  0x08); // 32: interrupt status
62__SINIC_REG32(IntrMask,    0x0c); // 32: interrupt mask
63__SINIC_REG32(RxMaxCopy,   0x10); // 32: max bytes per rx copy
64__SINIC_REG32(TxMaxCopy,   0x14); // 32: max bytes per tx copy
65__SINIC_REG32(RxMaxIntr,   0x18); // 32: max receives per interrupt
66__SINIC_REG32(Reserved0,   0x1c); // 32: reserved
67__SINIC_REG32(RxFifoSize,  0x20); // 32: rx fifo capacity in bytes
68__SINIC_REG32(TxFifoSize,  0x24); // 32: tx fifo capacity in bytes
69__SINIC_REG32(RxFifoMark,  0x28); // 32: rx fifo high watermark
70__SINIC_REG32(TxFifoMark,  0x2c); // 32: tx fifo low watermark
71__SINIC_REG32(RxData,      0x30); // 64: receive data
72__SINIC_REG32(RxDone,      0x38); // 64: receive done
73__SINIC_REG32(RxWait,      0x40); // 64: receive done (busy wait)
74__SINIC_REG32(TxData,      0x48); // 64: transmit data
75__SINIC_REG32(TxDone,      0x50); // 64: transmit done
76__SINIC_REG32(TxWait,      0x58); // 64: transmit done (busy wait)
77__SINIC_REG32(HwAddr,      0x60); // 64: mac address
78__SINIC_REG32(Size,        0x68); // register addres space size
79
80// Config register bits
81__SINIC_VAL32(Config_Thread,  8, 1); // enable receive filter
82__SINIC_VAL32(Config_Filter,  7, 1); // enable receive filter
83__SINIC_VAL32(Config_Vlan,    6, 1); // enable vlan tagging
84__SINIC_VAL32(Config_Virtual, 5, 1); // enable virtual addressing
85__SINIC_VAL32(Config_Desc,    4, 1); // enable tx/rx descriptors
86__SINIC_VAL32(Config_Poll,    3, 1); // enable polling
87__SINIC_VAL32(Config_IntEn,   2, 1); // enable interrupts
88__SINIC_VAL32(Config_TxEn,    1, 1); // enable transmit
89__SINIC_VAL32(Config_RxEn,    0, 1); // enable receive
90
91// Command register bits
92__SINIC_VAL32(Command_Reset, 0, 1); // reset chip
93
94// Interrupt register bits
95__SINIC_VAL32(Intr_TxLow,     7, 1); // tx fifo dropped below watermark
96__SINIC_VAL32(Intr_TxFull,    6, 1); // tx fifo full
97__SINIC_VAL32(Intr_TxDMA,     5, 1); // tx dma completed w/ interrupt
98__SINIC_VAL32(Intr_TxPacket,  4, 1); // packet transmitted
99__SINIC_VAL32(Intr_RxHigh,    3, 1); // rx fifo above high watermark
100__SINIC_VAL32(Intr_RxEmpty,   2, 1); // rx fifo empty
101__SINIC_VAL32(Intr_RxDMA,     1, 1); // rx dma completed w/ interrupt
102__SINIC_VAL32(Intr_RxPacket,  0, 1); // packet received
103__SINIC_REG32(Intr_All,       0xff); // all valid interrupts
104__SINIC_REG32(Intr_NoDelay,   0xcc); // interrupts that shouldn't be coalesced
105__SINIC_REG32(Intr_Res,      ~0xff); // reserved interrupt bits
106
107// RX Data Description
108__SINIC_VAL64(RxData_Len, 40, 20); // 0 - 1M
109__SINIC_VAL64(RxData_Addr, 0, 40); // Address 1TB
110
111// TX Data Description
112__SINIC_VAL64(TxData_More,     63,  1); // Packet not complete (will dma more)
113__SINIC_VAL64(TxData_Checksum, 62,  1); // do checksum
114__SINIC_VAL64(TxData_Len,      40, 20); // 0 - 1M
115__SINIC_VAL64(TxData_Addr,      0, 40); // Address 1TB
116
117// RX Done/Busy Information
118__SINIC_VAL64(RxDone_Packets,   32, 16); // number of packets in rx fifo
119__SINIC_VAL64(RxDone_Busy,      31,  1); // receive dma busy copying
120__SINIC_VAL64(RxDone_Complete,  30,  1); // valid data (packet complete)
121__SINIC_VAL64(RxDone_More,      29,  1); // Packet has more data (dma again)
122__SINIC_VAL64(RxDone_TcpError,  25,  1); // TCP packet error (bad checksum)
123__SINIC_VAL64(RxDone_UdpError,  24,  1); // UDP packet error (bad checksum)
124__SINIC_VAL64(RxDone_IpError,   23,  1); // IP packet error (bad checksum)
125__SINIC_VAL64(RxDone_TcpPacket, 22,  1); // this is a TCP packet
126__SINIC_VAL64(RxDone_UdpPacket, 21,  1); // this is a UDP packet
127__SINIC_VAL64(RxDone_IpPacket,  20,  1); // this is an IP packet
128__SINIC_VAL64(RxDone_CopyLen,    0, 20); // up to 256k
129
130// TX Done/Busy Information
131__SINIC_VAL64(TxDone_Packets,   32, 16); // number of packets in tx fifo
132__SINIC_VAL64(TxDone_Busy,      31,  1); // transmit dma busy copying
133__SINIC_VAL64(TxDone_Complete,  30,  1); // valid data (packet complete)
134__SINIC_VAL64(TxDone_Full,      29,  1); // tx fifo is full
135__SINIC_VAL64(TxDone_Low,       28,  1); // tx fifo is below the watermark
136__SINIC_VAL64(TxDone_CopyLen,    0, 20); // up to 256k
137
138struct Info
139{
140    uint8_t size;
141    bool read;
142    bool write;
143    bool delay_read;
144    bool delay_write;
145    const char *name;
146};
147
148/* namespace Regs */ }
149
150inline const Regs::Info&
151regInfo(Addr daddr)
152{
153    static Regs::Info invalid = { 0, false, false, false, false, "invalid" };
154    static Regs::Info info [] = {
155        { 4, true,  true,  false, false, "Config"     },
156        { 4, false, true,  false, false, "Command"    },
157        { 4, true,  true,  false, false, "IntrStatus" },
158        { 4, true,  true,  false, false, "IntrMask"   },
159        { 4, true,  false, false, false, "RxMaxCopy"  },
160        { 4, true,  false, false, false, "TxMaxCopy"  },
161        { 4, true,  false, false, false, "RxMaxIntr"  },
162        invalid,
163        { 4, true,  false, false, false, "RxFifoSize" },
164        { 4, true,  false, false, false, "TxFifoSize" },
165        { 4, true,  false, false, false, "RxFifoMark" },
166        { 4, true,  false, false, false, "TxFifoMark" },
167        { 8, true,  true,  false, true,  "RxData"     },
168        invalid,
169        { 8, true,  false, false, false, "RxDone"     },
170        invalid,
171        { 8, true,  false, false, false, "RxWait"     },
172        invalid,
173        { 8, true,  true,  false, true,  "TxData"     },
174        invalid,
175        { 8, true,  false, false, false, "TxDone"     },
176        invalid,
177        { 8, true,  false, false, false, "TxWait"     },
178        invalid,
179        { 8, true,  false, false, false, "HwAddr"     },
180        invalid,
181    };
182
183    return info[daddr / 4];
184}
185
186inline bool
187regValid(Addr daddr)
188{
189    if (daddr > Regs::Size)
190        return false;
191
192    if (regInfo(daddr).size == 0)
193        return false;
194
195    return true;
196}
197
198/* namespace Sinic */ }
199
200#endif // __DEV_SINICREG_HH__
201