sinicreg.hh revision 11263
11156SN/A/* 21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31156SN/A * All rights reserved. 41156SN/A * 51156SN/A * Redistribution and use in source and binary forms, with or without 61156SN/A * modification, are permitted provided that the following conditions are 71156SN/A * met: redistributions of source code must retain the above copyright 81156SN/A * notice, this list of conditions and the following disclaimer; 91156SN/A * redistributions in binary form must reproduce the above copyright 101156SN/A * notice, this list of conditions and the following disclaimer in the 111156SN/A * documentation and/or other materials provided with the distribution; 121156SN/A * neither the name of the copyright holders nor the names of its 131156SN/A * contributors may be used to endorse or promote products derived from 141156SN/A * this software without specific prior written permission. 151156SN/A * 161156SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171156SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181156SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191156SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201156SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211156SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221156SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231156SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241156SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251156SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261156SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282665SN/A * Authors: Nathan Binkert 291156SN/A */ 301156SN/A 3111263Sandreas.sandberg@arm.com#ifndef __DEV_NET_SINICREG_HH__ 3211263Sandreas.sandberg@arm.com#define __DEV_NET_SINICREG_HH__ 331156SN/A 348902SN/A#define __SINIC_REG32(NAME, VAL) static const uint32_t NAME = (VAL); 358902SN/A#define __SINIC_REG64(NAME, VAL) static const uint64_t NAME = (VAL); 361156SN/A 371156SN/A#define __SINIC_VAL32(NAME, OFFSET, WIDTH) \ 381156SN/A static const uint32_t NAME##_width = WIDTH; \ 391156SN/A static const uint32_t NAME##_offset = OFFSET; \ 401156SN/A static const uint32_t NAME##_mask = (1 << WIDTH) - 1; \ 411156SN/A static const uint32_t NAME = ((1 << WIDTH) - 1) << OFFSET; \ 421156SN/A static inline uint32_t get_##NAME(uint32_t reg) \ 431156SN/A { return (reg & NAME) >> OFFSET; } \ 441156SN/A static inline uint32_t set_##NAME(uint32_t reg, uint32_t val) \ 451156SN/A { return (reg & ~NAME) | ((val << OFFSET) & NAME); } 461156SN/A 471156SN/A#define __SINIC_VAL64(NAME, OFFSET, WIDTH) \ 481156SN/A static const uint64_t NAME##_width = WIDTH; \ 491156SN/A static const uint64_t NAME##_offset = OFFSET; \ 501156SN/A static const uint64_t NAME##_mask = (ULL(1) << WIDTH) - 1; \ 515543SN/A static const uint64_t NAME = ((ULL(1) << WIDTH) - 1) << OFFSET; \ 521156SN/A static inline uint64_t get_##NAME(uint64_t reg) \ 531156SN/A { return (reg & NAME) >> OFFSET; } \ 541156SN/A static inline uint64_t set_##NAME(uint64_t reg, uint64_t val) \ 551156SN/A { return (reg & ~NAME) | ((val << OFFSET) & NAME); } 561156SN/A 571156SN/Anamespace Sinic { 581156SN/Anamespace Regs { 591156SN/A 602282SN/Astatic const int VirtualShift = 8; 612008SN/Astatic const int VirtualMask = 0xff; 622008SN/A 631156SN/A// Registers 648902SN/A__SINIC_REG32(Config, 0x00) // 32: configuration register 658902SN/A__SINIC_REG32(Command, 0x04) // 32: command register 668902SN/A__SINIC_REG32(IntrStatus, 0x08) // 32: interrupt status 678902SN/A__SINIC_REG32(IntrMask, 0x0c) // 32: interrupt mask 688902SN/A__SINIC_REG32(RxMaxCopy, 0x10) // 32: max bytes per rx copy 698902SN/A__SINIC_REG32(TxMaxCopy, 0x14) // 32: max bytes per tx copy 708902SN/A__SINIC_REG32(ZeroCopySize, 0x18) // 32: bytes to copy if below threshold 718902SN/A__SINIC_REG32(ZeroCopyMark, 0x1c) // 32: only zero-copy above this threshold 728902SN/A__SINIC_REG32(VirtualCount, 0x20) // 32: number of virutal NICs 738902SN/A__SINIC_REG32(RxMaxIntr, 0x24) // 32: max receives per interrupt 748902SN/A__SINIC_REG32(RxFifoSize, 0x28) // 32: rx fifo capacity in bytes 758902SN/A__SINIC_REG32(TxFifoSize, 0x2c) // 32: tx fifo capacity in bytes 768902SN/A__SINIC_REG32(RxFifoLow, 0x30) // 32: rx fifo low watermark 778902SN/A__SINIC_REG32(TxFifoLow, 0x34) // 32: tx fifo low watermark 788902SN/A__SINIC_REG32(RxFifoHigh, 0x38) // 32: rx fifo high watermark 798902SN/A__SINIC_REG32(TxFifoHigh, 0x3c) // 32: tx fifo high watermark 808902SN/A__SINIC_REG32(RxData, 0x40) // 64: receive data 818902SN/A__SINIC_REG32(RxDone, 0x48) // 64: receive done 828902SN/A__SINIC_REG32(RxWait, 0x50) // 64: receive done (busy wait) 838902SN/A__SINIC_REG32(TxData, 0x58) // 64: transmit data 848902SN/A__SINIC_REG32(TxDone, 0x60) // 64: transmit done 858902SN/A__SINIC_REG32(TxWait, 0x68) // 64: transmit done (busy wait) 868902SN/A__SINIC_REG32(HwAddr, 0x70) // 64: mac address 878902SN/A__SINIC_REG32(RxStatus, 0x78) 888902SN/A__SINIC_REG32(Size, 0x80) // register addres space size 891156SN/A 901156SN/A// Config register bits 918902SN/A__SINIC_VAL32(Config_ZeroCopy, 12, 1) // enable zero copy 928902SN/A__SINIC_VAL32(Config_DelayCopy,11, 1) // enable delayed copy 938902SN/A__SINIC_VAL32(Config_RSS, 10, 1) // enable receive side scaling 948902SN/A__SINIC_VAL32(Config_RxThread, 9, 1) // enable receive threads 958902SN/A__SINIC_VAL32(Config_TxThread, 8, 1) // enable transmit thread 968902SN/A__SINIC_VAL32(Config_Filter, 7, 1) // enable receive filter 978902SN/A__SINIC_VAL32(Config_Vlan, 6, 1) // enable vlan tagging 988902SN/A__SINIC_VAL32(Config_Vaddr, 5, 1) // enable virtual addressing 998902SN/A__SINIC_VAL32(Config_Desc, 4, 1) // enable tx/rx descriptors 1008902SN/A__SINIC_VAL32(Config_Poll, 3, 1) // enable polling 1018902SN/A__SINIC_VAL32(Config_IntEn, 2, 1) // enable interrupts 1028902SN/A__SINIC_VAL32(Config_TxEn, 1, 1) // enable transmit 1038902SN/A__SINIC_VAL32(Config_RxEn, 0, 1) // enable receive 1041156SN/A 1051939SN/A// Command register bits 1068902SN/A__SINIC_VAL32(Command_Intr, 1, 1) // software interrupt 1078902SN/A__SINIC_VAL32(Command_Reset, 0, 1) // reset chip 1081939SN/A 1091156SN/A// Interrupt register bits 1108902SN/A__SINIC_VAL32(Intr_Soft, 8, 1) // software interrupt 1118902SN/A__SINIC_VAL32(Intr_TxLow, 7, 1) // tx fifo dropped below watermark 1128902SN/A__SINIC_VAL32(Intr_TxFull, 6, 1) // tx fifo full 1138902SN/A__SINIC_VAL32(Intr_TxDMA, 5, 1) // tx dma completed w/ interrupt 1148902SN/A__SINIC_VAL32(Intr_TxPacket, 4, 1) // packet transmitted 1158902SN/A__SINIC_VAL32(Intr_RxHigh, 3, 1) // rx fifo above high watermark 1168902SN/A__SINIC_VAL32(Intr_RxEmpty, 2, 1) // rx fifo empty 1178902SN/A__SINIC_VAL32(Intr_RxDMA, 1, 1) // rx dma completed w/ interrupt 1188902SN/A__SINIC_VAL32(Intr_RxPacket, 0, 1) // packet received 1198902SN/A__SINIC_REG32(Intr_All, 0x01ff) // all valid interrupts 1208902SN/A__SINIC_REG32(Intr_NoDelay, 0x01cc) // interrupts that aren't coalesced 1218902SN/A__SINIC_REG32(Intr_Res, ~0x01ff) // reserved interrupt bits 1221156SN/A 1231156SN/A// RX Data Description 1248902SN/A__SINIC_VAL64(RxData_NoDelay, 61, 1) // Don't Delay this copy 1258902SN/A__SINIC_VAL64(RxData_Vaddr, 60, 1) // Addr is virtual 1268902SN/A__SINIC_VAL64(RxData_Len, 40, 20) // 0 - 256k 1278902SN/A__SINIC_VAL64(RxData_Addr, 0, 40) // Address 1TB 1281156SN/A 1291156SN/A// TX Data Description 1308902SN/A__SINIC_VAL64(TxData_More, 63, 1) // Packet not complete (will dma more) 1318902SN/A__SINIC_VAL64(TxData_Checksum, 62, 1) // do checksum 1328902SN/A__SINIC_VAL64(TxData_Vaddr, 60, 1) // Addr is virtual 1338902SN/A__SINIC_VAL64(TxData_Len, 40, 20) // 0 - 256k 1348902SN/A__SINIC_VAL64(TxData_Addr, 0, 40) // Address 1TB 1351156SN/A 1361156SN/A// RX Done/Busy Information 1378902SN/A__SINIC_VAL64(RxDone_Packets, 32, 16) // number of packets in rx fifo 1388902SN/A__SINIC_VAL64(RxDone_Busy, 31, 1) // receive dma busy copying 1398902SN/A__SINIC_VAL64(RxDone_Complete, 30, 1) // valid data (packet complete) 1408902SN/A__SINIC_VAL64(RxDone_More, 29, 1) // Packet has more data (dma again) 1418902SN/A__SINIC_VAL64(RxDone_Empty, 28, 1) // rx fifo is empty 1428902SN/A__SINIC_VAL64(RxDone_High, 27, 1) // rx fifo is above the watermark 1438902SN/A__SINIC_VAL64(RxDone_NotHigh, 26, 1) // rxfifo never hit the high watermark 1448902SN/A__SINIC_VAL64(RxDone_TcpError, 25, 1) // TCP packet error (bad checksum) 1458902SN/A__SINIC_VAL64(RxDone_UdpError, 24, 1) // UDP packet error (bad checksum) 1468902SN/A__SINIC_VAL64(RxDone_IpError, 23, 1) // IP packet error (bad checksum) 1478902SN/A__SINIC_VAL64(RxDone_TcpPacket, 22, 1) // this is a TCP packet 1488902SN/A__SINIC_VAL64(RxDone_UdpPacket, 21, 1) // this is a UDP packet 1498902SN/A__SINIC_VAL64(RxDone_IpPacket, 20, 1) // this is an IP packet 1508902SN/A__SINIC_VAL64(RxDone_CopyLen, 0, 20) // up to 256k 1511156SN/A 1521156SN/A// TX Done/Busy Information 1538902SN/A__SINIC_VAL64(TxDone_Packets, 32, 16) // number of packets in tx fifo 1548902SN/A__SINIC_VAL64(TxDone_Busy, 31, 1) // transmit dma busy copying 1558902SN/A__SINIC_VAL64(TxDone_Complete, 30, 1) // valid data (packet complete) 1568902SN/A__SINIC_VAL64(TxDone_Full, 29, 1) // tx fifo is full 1578902SN/A__SINIC_VAL64(TxDone_Low, 28, 1) // tx fifo is below the watermark 1588902SN/A__SINIC_VAL64(TxDone_Res0, 27, 1) // reserved 1598902SN/A__SINIC_VAL64(TxDone_Res1, 26, 1) // reserved 1608902SN/A__SINIC_VAL64(TxDone_Res2, 25, 1) // reserved 1618902SN/A__SINIC_VAL64(TxDone_Res3, 24, 1) // reserved 1628902SN/A__SINIC_VAL64(TxDone_Res4, 23, 1) // reserved 1638902SN/A__SINIC_VAL64(TxDone_Res5, 22, 1) // reserved 1648902SN/A__SINIC_VAL64(TxDone_Res6, 21, 1) // reserved 1658902SN/A__SINIC_VAL64(TxDone_Res7, 20, 1) // reserved 1668902SN/A__SINIC_VAL64(TxDone_CopyLen, 0, 20) // up to 256k 1671156SN/A 1688902SN/A__SINIC_VAL64(RxStatus_Dirty, 48, 16) 1698902SN/A__SINIC_VAL64(RxStatus_Mapped, 32, 16) 1708902SN/A__SINIC_VAL64(RxStatus_Busy, 16, 16) 1718902SN/A__SINIC_VAL64(RxStatus_Head, 0, 16) 1725603SN/A 1731939SN/Astruct Info 1741156SN/A{ 1751939SN/A uint8_t size; 1761939SN/A bool read; 1771939SN/A bool write; 1781939SN/A const char *name; 1791939SN/A}; 1801939SN/A 1817811SN/A} // namespace Regs 1821939SN/A 1831939SN/Ainline const Regs::Info& 1842130SN/AregInfo(Addr daddr) 1851939SN/A{ 1862126SN/A static Regs::Info invalid = { 0, false, false, "invalid" }; 1871939SN/A static Regs::Info info [] = { 1885603SN/A { 4, true, true, "Config" }, 1895603SN/A { 4, false, true, "Command" }, 1905603SN/A { 4, true, true, "IntrStatus" }, 1915603SN/A { 4, true, true, "IntrMask" }, 1925603SN/A { 4, true, false, "RxMaxCopy" }, 1935603SN/A { 4, true, false, "TxMaxCopy" }, 1945603SN/A { 4, true, false, "ZeroCopySize" }, 1955603SN/A { 4, true, false, "ZeroCopyMark" }, 1965603SN/A { 4, true, false, "VirtualCount" }, 1975603SN/A { 4, true, false, "RxMaxIntr" }, 1985603SN/A { 4, true, false, "RxFifoSize" }, 1995603SN/A { 4, true, false, "TxFifoSize" }, 2005603SN/A { 4, true, false, "RxFifoLow" }, 2015603SN/A { 4, true, false, "TxFifoLow" }, 2025603SN/A { 4, true, false, "RxFifoHigh" }, 2035603SN/A { 4, true, false, "TxFifoHigh" }, 2045603SN/A { 8, true, true, "RxData" }, 2051997SN/A invalid, 2065603SN/A { 8, true, false, "RxDone" }, 2071997SN/A invalid, 2085603SN/A { 8, true, false, "RxWait" }, 2091997SN/A invalid, 2105603SN/A { 8, true, true, "TxData" }, 2111997SN/A invalid, 2125603SN/A { 8, true, false, "TxDone" }, 2131997SN/A invalid, 2145603SN/A { 8, true, false, "TxWait" }, 2151997SN/A invalid, 2165603SN/A { 8, true, false, "HwAddr" }, 2175603SN/A invalid, 2185603SN/A { 8, true, false, "RxStatus" }, 2191997SN/A invalid, 2201156SN/A }; 2211156SN/A 2221939SN/A return info[daddr / 4]; 2231156SN/A} 2241156SN/A 2251939SN/Ainline bool 2262130SN/AregValid(Addr daddr) 2271156SN/A{ 2281939SN/A if (daddr > Regs::Size) 2291939SN/A return false; 2301156SN/A 2311939SN/A if (regInfo(daddr).size == 0) 2321939SN/A return false; 2331156SN/A 2341939SN/A return true; 2351156SN/A} 2361156SN/A 2377811SN/A} // namespace Sinic 2381156SN/A 23911263Sandreas.sandberg@arm.com#endif // __DEV_NET_SINICREG_HH__ 240