Ethernet.py revision 4597
1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 29from m5.SimObject import SimObject 30from m5.params import * 31from m5.proxy import * 32from Pci import PciDevice, PciConfigData 33 34class EtherInt(SimObject): 35 type = 'EtherInt' 36 abstract = True 37 peer = Param.EtherInt(NULL, "peer interface") 38 39class EtherLink(SimObject): 40 type = 'EtherLink' 41 int1 = Param.EtherInt("interface 1") 42 int2 = Param.EtherInt("interface 2") 43 delay = Param.Latency('0us', "packet transmit delay") 44 delay_var = Param.Latency('0ns', "packet transmit delay variability") 45 speed = Param.NetworkBandwidth('1Gbps', "link speed") 46 dump = Param.EtherDump(NULL, "dump object") 47 48class EtherBus(SimObject): 49 type = 'EtherBus' 50 loopback = Param.Bool(True, "send packet back to the sending interface") 51 dump = Param.EtherDump(NULL, "dump object") 52 speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") 53 54class EtherTap(EtherInt): 55 type = 'EtherTap' 56 bufsz = Param.Int(10000, "tap buffer size") 57 dump = Param.EtherDump(NULL, "dump object") 58 port = Param.UInt16(3500, "tap port") 59 60class EtherDump(SimObject): 61 type = 'EtherDump' 62 file = Param.String("dump file") 63 maxlen = Param.Int(96, "max portion of packet data to dump") 64 65class IGbE(PciDevice): 66 type = 'IGbE' 67 hardware_address = Param.EthernetAddr(NextEthernetAddr, 68 "Ethernet Hardware Address") 69 use_flow_control = Param.Bool(False, 70 "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") 71 rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") 72 tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") 73 rx_desc_cache_size = Param.Int(64, 74 "Number of enteries in the rx descriptor cache") 75 tx_desc_cache_size = Param.Int(64, 76 "Number of enteries in the rx descriptor cache") 77 clock = Param.Clock('500MHz', "Clock speed of the device") 78 79class IGbEPciData(PciConfigData): 80 VendorID = 0x8086 81 DeviceID = 0x1075 82 SubsystemID = 0x1008 83 SubsystemVendorID = 0x8086 84 Status = 0x0000 85 SubClassCode = 0x00 86 ClassCode = 0x02 87 ProgIF = 0x00 88 BAR0 = 0x00000000 89 BAR1 = 0x00000000 90 BAR2 = 0x00000000 91 BAR3 = 0x00000000 92 BAR4 = 0x00000000 93 BAR5 = 0x00000000 94 MaximumLatency = 0x00 95 MinimumGrant = 0xff 96 InterruptLine = 0x1e 97 InterruptPin = 0x01 98 BAR0Size = '128kB' 99 100class IGbEInt(EtherInt): 101 type = 'IGbEInt' 102 device = Param.IGbE("Ethernet device of this interface") 103 104class EtherDevBase(PciDevice): 105 type = 'EtherDevBase' 106 abstract = True 107 hardware_address = Param.EthernetAddr(NextEthernetAddr, 108 "Ethernet Hardware Address") 109 110 clock = Param.Clock('0ns', "State machine processor frequency") 111 112 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") 113 dma_read_factor = Param.Latency('0us', "multiplier for dma reads") 114 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") 115 dma_write_factor = Param.Latency('0us', "multiplier for dma writes") 116 117 rx_delay = Param.Latency('1us', "Receive Delay") 118 tx_delay = Param.Latency('1us', "Transmit Delay") 119 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") 120 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") 121 122 rx_filter = Param.Bool(True, "Enable Receive Filter") 123 intr_delay = Param.Latency('10us', "Interrupt propagation delay") 124 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") 125 tx_thread = Param.Bool(False, "dedicated kernel threads for receive") 126 rss = Param.Bool(False, "Receive Side Scaling") 127 128class NSGigEPciData(PciConfigData): 129 VendorID = 0x100B 130 DeviceID = 0x0022 131 Status = 0x0290 132 SubClassCode = 0x00 133 ClassCode = 0x02 134 ProgIF = 0x00 135 BAR0 = 0x00000001 136 BAR1 = 0x00000000 137 BAR2 = 0x00000000 138 BAR3 = 0x00000000 139 BAR4 = 0x00000000 140 BAR5 = 0x00000000 141 MaximumLatency = 0x34 142 MinimumGrant = 0xb0 143 InterruptLine = 0x1e 144 InterruptPin = 0x01 145 BAR0Size = '256B' 146 BAR1Size = '4kB' 147 148class NSGigE(EtherDevBase): 149 type = 'NSGigE' 150 151 dma_data_free = Param.Bool(False, "DMA of Data is free") 152 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") 153 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") 154 155 configdata = NSGigEPciData() 156 157 158class NSGigEInt(EtherInt): 159 type = 'NSGigEInt' 160 device = Param.NSGigE("Ethernet device of this interface") 161 162class SinicPciData(PciConfigData): 163 VendorID = 0x1291 164 DeviceID = 0x1293 165 Status = 0x0290 166 SubClassCode = 0x00 167 ClassCode = 0x02 168 ProgIF = 0x00 169 BAR0 = 0x00000000 170 BAR1 = 0x00000000 171 BAR2 = 0x00000000 172 BAR3 = 0x00000000 173 BAR4 = 0x00000000 174 BAR5 = 0x00000000 175 MaximumLatency = 0x34 176 MinimumGrant = 0xb0 177 InterruptLine = 0x1e 178 InterruptPin = 0x01 179 BAR0Size = '64kB' 180 181class Sinic(EtherDevBase): 182 type = 'Sinic' 183 184 rx_max_copy = Param.MemorySize('1514B', "rx max copy") 185 tx_max_copy = Param.MemorySize('16kB', "tx max copy") 186 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") 187 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") 188 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") 189 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") 190 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") 191 virtual_count = Param.UInt32(1, "Virtualized SINIC") 192 zero_copy = Param.Bool(False, "Zero copy receive") 193 delay_copy = Param.Bool(False, "Delayed copy transmit") 194 virtual_addr = Param.Bool(False, "Virtual addressing") 195 196 configdata = SinicPciData() 197 198class SinicInt(EtherInt): 199 type = 'SinicInt' 200 device = Param.Sinic("Ethernet device of this interface") 201