Ethernet.py revision 4597
11046SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 21046SN/A# All rights reserved. 31762SN/A# 41046SN/A# Redistribution and use in source and binary forms, with or without 51046SN/A# modification, are permitted provided that the following conditions are 61046SN/A# met: redistributions of source code must retain the above copyright 71046SN/A# notice, this list of conditions and the following disclaimer; 81046SN/A# redistributions in binary form must reproduce the above copyright 91046SN/A# notice, this list of conditions and the following disclaimer in the 101046SN/A# documentation and/or other materials provided with the distribution; 111046SN/A# neither the name of the copyright holders nor the names of its 121046SN/A# contributors may be used to endorse or promote products derived from 131046SN/A# this software without specific prior written permission. 141046SN/A# 151046SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 161046SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 171046SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 181046SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 191046SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 201046SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 211046SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 221046SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 231046SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 241046SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 251046SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 261046SN/A# 271046SN/A# Authors: Nathan Binkert 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edufrom m5.SimObject import SimObject 302665Ssaidi@eecs.umich.edufrom m5.params import * 311046SN/Afrom m5.proxy import * 321530SN/Afrom Pci import PciDevice, PciConfigData 332655Sstever@eecs.umich.edu 342655Sstever@eecs.umich.educlass EtherInt(SimObject): 352655Sstever@eecs.umich.edu type = 'EtherInt' 362655Sstever@eecs.umich.edu abstract = True 372655Sstever@eecs.umich.edu peer = Param.EtherInt(NULL, "peer interface") 381530SN/A 391530SN/Aclass EtherLink(SimObject): 401530SN/A type = 'EtherLink' 412655Sstever@eecs.umich.edu int1 = Param.EtherInt("interface 1") 421046SN/A int2 = Param.EtherInt("interface 2") 432655Sstever@eecs.umich.edu delay = Param.Latency('0us', "packet transmit delay") 442655Sstever@eecs.umich.edu delay_var = Param.Latency('0ns', "packet transmit delay variability") 452655Sstever@eecs.umich.edu speed = Param.NetworkBandwidth('1Gbps', "link speed") 461046SN/A dump = Param.EtherDump(NULL, "dump object") 472655Sstever@eecs.umich.edu 482655Sstever@eecs.umich.educlass EtherBus(SimObject): 492655Sstever@eecs.umich.edu type = 'EtherBus' 502655Sstever@eecs.umich.edu loopback = Param.Bool(True, "send packet back to the sending interface") 512655Sstever@eecs.umich.edu dump = Param.EtherDump(NULL, "dump object") 521046SN/A speed = Param.NetworkBandwidth('100Mbps', "bus speed in bits per second") 532655Sstever@eecs.umich.edu 542655Sstever@eecs.umich.educlass EtherTap(EtherInt): 552655Sstever@eecs.umich.edu type = 'EtherTap' 562655Sstever@eecs.umich.edu bufsz = Param.Int(10000, "tap buffer size") 571046SN/A dump = Param.EtherDump(NULL, "dump object") 582655Sstever@eecs.umich.edu port = Param.UInt16(3500, "tap port") 592655Sstever@eecs.umich.edu 602655Sstever@eecs.umich.educlass EtherDump(SimObject): 612655Sstever@eecs.umich.edu type = 'EtherDump' 622655Sstever@eecs.umich.edu file = Param.String("dump file") 632655Sstever@eecs.umich.edu maxlen = Param.Int(96, "max portion of packet data to dump") 642655Sstever@eecs.umich.edu 652655Sstever@eecs.umich.educlass IGbE(PciDevice): 662655Sstever@eecs.umich.edu type = 'IGbE' 672655Sstever@eecs.umich.edu hardware_address = Param.EthernetAddr(NextEthernetAddr, 682655Sstever@eecs.umich.edu "Ethernet Hardware Address") 692655Sstever@eecs.umich.edu use_flow_control = Param.Bool(False, 701046SN/A "Should we use xon/xoff flow contorl (UNIMPLEMENTD)") 712655Sstever@eecs.umich.edu rx_fifo_size = Param.MemorySize('384kB', "Size of the rx FIFO") 722655Sstever@eecs.umich.edu tx_fifo_size = Param.MemorySize('384kB', "Size of the tx FIFO") 732655Sstever@eecs.umich.edu rx_desc_cache_size = Param.Int(64, 742655Sstever@eecs.umich.edu "Number of enteries in the rx descriptor cache") 752655Sstever@eecs.umich.edu tx_desc_cache_size = Param.Int(64, 762655Sstever@eecs.umich.edu "Number of enteries in the rx descriptor cache") 771046SN/A clock = Param.Clock('500MHz', "Clock speed of the device") 782655Sstever@eecs.umich.edu 791046SN/Aclass IGbEPciData(PciConfigData): 802655Sstever@eecs.umich.edu VendorID = 0x8086 812655Sstever@eecs.umich.edu DeviceID = 0x1075 821439SN/A SubsystemID = 0x1008 831530SN/A SubsystemVendorID = 0x8086 841530SN/A Status = 0x0000 851530SN/A SubClassCode = 0x00 861858SN/A ClassCode = 0x02 871530SN/A ProgIF = 0x00 881439SN/A BAR0 = 0x00000000 891858SN/A BAR1 = 0x00000000 901858SN/A BAR2 = 0x00000000 911858SN/A BAR3 = 0x00000000 922655Sstever@eecs.umich.edu BAR4 = 0x00000000 932655Sstever@eecs.umich.edu BAR5 = 0x00000000 942655Sstever@eecs.umich.edu MaximumLatency = 0x00 952655Sstever@eecs.umich.edu MinimumGrant = 0xff 962655Sstever@eecs.umich.edu InterruptLine = 0x1e 972655Sstever@eecs.umich.edu InterruptPin = 0x01 982655Sstever@eecs.umich.edu BAR0Size = '128kB' 992655Sstever@eecs.umich.edu 1002655Sstever@eecs.umich.educlass IGbEInt(EtherInt): 1012655Sstever@eecs.umich.edu type = 'IGbEInt' 1022655Sstever@eecs.umich.edu device = Param.IGbE("Ethernet device of this interface") 1032655Sstever@eecs.umich.edu 1042655Sstever@eecs.umich.educlass EtherDevBase(PciDevice): 1052655Sstever@eecs.umich.edu type = 'EtherDevBase' 1062655Sstever@eecs.umich.edu abstract = True 107 hardware_address = Param.EthernetAddr(NextEthernetAddr, 108 "Ethernet Hardware Address") 109 110 clock = Param.Clock('0ns', "State machine processor frequency") 111 112 dma_read_delay = Param.Latency('0us', "fixed delay for dma reads") 113 dma_read_factor = Param.Latency('0us', "multiplier for dma reads") 114 dma_write_delay = Param.Latency('0us', "fixed delay for dma writes") 115 dma_write_factor = Param.Latency('0us', "multiplier for dma writes") 116 117 rx_delay = Param.Latency('1us', "Receive Delay") 118 tx_delay = Param.Latency('1us', "Transmit Delay") 119 rx_fifo_size = Param.MemorySize('512kB', "max size of rx fifo") 120 tx_fifo_size = Param.MemorySize('512kB', "max size of tx fifo") 121 122 rx_filter = Param.Bool(True, "Enable Receive Filter") 123 intr_delay = Param.Latency('10us', "Interrupt propagation delay") 124 rx_thread = Param.Bool(False, "dedicated kernel thread for transmit") 125 tx_thread = Param.Bool(False, "dedicated kernel threads for receive") 126 rss = Param.Bool(False, "Receive Side Scaling") 127 128class NSGigEPciData(PciConfigData): 129 VendorID = 0x100B 130 DeviceID = 0x0022 131 Status = 0x0290 132 SubClassCode = 0x00 133 ClassCode = 0x02 134 ProgIF = 0x00 135 BAR0 = 0x00000001 136 BAR1 = 0x00000000 137 BAR2 = 0x00000000 138 BAR3 = 0x00000000 139 BAR4 = 0x00000000 140 BAR5 = 0x00000000 141 MaximumLatency = 0x34 142 MinimumGrant = 0xb0 143 InterruptLine = 0x1e 144 InterruptPin = 0x01 145 BAR0Size = '256B' 146 BAR1Size = '4kB' 147 148class NSGigE(EtherDevBase): 149 type = 'NSGigE' 150 151 dma_data_free = Param.Bool(False, "DMA of Data is free") 152 dma_desc_free = Param.Bool(False, "DMA of Descriptors is free") 153 dma_no_allocate = Param.Bool(True, "Should we allocate cache on read") 154 155 configdata = NSGigEPciData() 156 157 158class NSGigEInt(EtherInt): 159 type = 'NSGigEInt' 160 device = Param.NSGigE("Ethernet device of this interface") 161 162class SinicPciData(PciConfigData): 163 VendorID = 0x1291 164 DeviceID = 0x1293 165 Status = 0x0290 166 SubClassCode = 0x00 167 ClassCode = 0x02 168 ProgIF = 0x00 169 BAR0 = 0x00000000 170 BAR1 = 0x00000000 171 BAR2 = 0x00000000 172 BAR3 = 0x00000000 173 BAR4 = 0x00000000 174 BAR5 = 0x00000000 175 MaximumLatency = 0x34 176 MinimumGrant = 0xb0 177 InterruptLine = 0x1e 178 InterruptPin = 0x01 179 BAR0Size = '64kB' 180 181class Sinic(EtherDevBase): 182 type = 'Sinic' 183 184 rx_max_copy = Param.MemorySize('1514B', "rx max copy") 185 tx_max_copy = Param.MemorySize('16kB', "tx max copy") 186 rx_max_intr = Param.UInt32(10, "max rx packets per interrupt") 187 rx_fifo_threshold = Param.MemorySize('384kB', "rx fifo high threshold") 188 rx_fifo_low_mark = Param.MemorySize('128kB', "rx fifo low threshold") 189 tx_fifo_high_mark = Param.MemorySize('384kB', "tx fifo high threshold") 190 tx_fifo_threshold = Param.MemorySize('128kB', "tx fifo low threshold") 191 virtual_count = Param.UInt32(1, "Virtualized SINIC") 192 zero_copy = Param.Bool(False, "Zero copy receive") 193 delay_copy = Param.Bool(False, "Delayed copy transmit") 194 virtual_addr = Param.Bool(False, "Virtual addressing") 195 196 configdata = SinicPciData() 197 198class SinicInt(EtherInt): 199 type = 'SinicInt' 200 device = Param.Sinic("Ethernet device of this interface") 201