malta.hh revision 5222:bb733a878f85
12381SN/A/*
22381SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
32381SN/A * All rights reserved.
42381SN/A *
52381SN/A * Redistribution and use in source and binary forms, with or without
62381SN/A * modification, are permitted provided that the following conditions are
72381SN/A * met: redistributions of source code must retain the above copyright
82381SN/A * notice, this list of conditions and the following disclaimer;
92381SN/A * redistributions in binary form must reproduce the above copyright
102381SN/A * notice, this list of conditions and the following disclaimer in the
112381SN/A * documentation and/or other materials provided with the distribution;
122381SN/A * neither the name of the copyright holders nor the names of its
132381SN/A * contributors may be used to endorse or promote products derived from
142381SN/A * this software without specific prior written permission.
152381SN/A *
162381SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172381SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182381SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192381SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202381SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212381SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222381SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232381SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242381SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252381SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262381SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272381SN/A *
282381SN/A * Authors: Ali Saidi
292381SN/A *          Rick Strong
302381SN/A */
312381SN/A
322381SN/A/**
332381SN/A * @file
342381SN/A * Declaration of top level class for the Malta chipset. This class just
352381SN/A * retains pointers to all its children so the children can communicate.
362381SN/A */
372381SN/A
382381SN/A#ifndef __DEV_MALTA_HH__
392381SN/A#define __DEV_MALTA_HH__
402381SN/A
412381SN/A#include "dev/platform.hh"
422381SN/A#include "params/Malta.hh"
432381SN/A
442439SN/Aclass IdeController;
452381SN/Aclass MaltaCChip;
462381SN/Aclass MaltaPChip;
472381SN/Aclass MaltaIO;
482381SN/Aclass System;
492407SN/A
502407SN/A/**
512407SN/A  * Top level class for Malta Chipset emulation.
522407SN/A  * This structure just contains pointers to all the
532407SN/A  * children so the children can commnicate to do the
542407SN/A  * read work
552407SN/A  */
562407SN/A
572521SN/Aclass Malta : public Platform
582407SN/A{
592381SN/A  public:
602381SN/A    /** Max number of CPUs in a Malta */
612381SN/A    static const int Max_CPUs = 64;
622381SN/A
632381SN/A    /** Pointer to the system */
642381SN/A    System *system;
652381SN/A
662381SN/A    /** Pointer to the MaltaIO device which has the RTC */
672381SN/A    MaltaIO *io;
682381SN/A
692381SN/A    /** Pointer to the Malta CChip.
702381SN/A     * The chip contains some configuration information and
712381SN/A     * all the interrupt mask and status registers
722640Sstever@eecs.umich.edu     */
732640Sstever@eecs.umich.edu    MaltaCChip *cchip;
742640Sstever@eecs.umich.edu
752640Sstever@eecs.umich.edu    /** Pointer to the Malta PChip.
762640Sstever@eecs.umich.edu     * The pchip is the interface to the PCI bus, in our case
772661Sstever@eecs.umich.edu     * it does not have to do much.
782661Sstever@eecs.umich.edu     */
792661Sstever@eecs.umich.edu    MaltaPChip *pchip;
802661Sstever@eecs.umich.edu
812661Sstever@eecs.umich.edu    int intr_sum_type[Malta::Max_CPUs];
822381SN/A    int ipi_pending[Malta::Max_CPUs];
832381SN/A
842640Sstever@eecs.umich.edu  public:
852640Sstever@eecs.umich.edu    /**
862640Sstever@eecs.umich.edu     * Constructor for the Malta Class.
872640Sstever@eecs.umich.edu     * @param name name of the object
882640Sstever@eecs.umich.edu     * @param s system the object belongs to
892640Sstever@eecs.umich.edu     * @param intctrl pointer to the interrupt controller
902640Sstever@eecs.umich.edu     */
912661Sstever@eecs.umich.edu    typedef MaltaParams Params;
922640Sstever@eecs.umich.edu    Malta(const Params *p);
932640Sstever@eecs.umich.edu
942640Sstever@eecs.umich.edu    /**
952640Sstever@eecs.umich.edu     * Return the interrupting frequency to MipsAccess
962640Sstever@eecs.umich.edu     * @return frequency of RTC interrupts
972474SN/A     */
982640Sstever@eecs.umich.edu    virtual Tick intrFrequency();
992381SN/A
1002657Ssaidi@eecs.umich.edu    /**
1012657Ssaidi@eecs.umich.edu     * Cause the cpu to post a serial interrupt to the CPU.
1022381SN/A     */
1032381SN/A    virtual void postConsoleInt();
1042381SN/A
1052381SN/A    /**
1062381SN/A     * Clear a posted CPU interrupt (id=55)
1072381SN/A     */
1082381SN/A    virtual void clearConsoleInt();
1092642Sstever@eecs.umich.edu
1102381SN/A    /**
1112642Sstever@eecs.umich.edu     * Cause the chipset to post a cpi interrupt to the CPU.
1122408SN/A     */
1132408SN/A    virtual void postPciInt(int line);
1142409SN/A
1152408SN/A    /**
1162381SN/A     * Clear a posted PCI->CPU interrupt
1172381SN/A     */
1182406SN/A    virtual void clearPciInt(int line);
1192406SN/A
1202406SN/A
1212381SN/A    virtual Addr pciToDma(Addr pciAddr) const;
1222630SN/A
1232381SN/A    /**
1242381SN/A     * Calculate the configuration address given a bus/dev/func.
1252630SN/A     */
1262381SN/A    virtual Addr calcConfigAddr(int bus, int dev, int func);
1272381SN/A
1282630SN/A    /**
1292381SN/A     * Serialize this object to the given output stream.
1302381SN/A     * @param os The stream to serialize to.
1312381SN/A     */
1322381SN/A    virtual void serialize(std::ostream &os);
1332381SN/A
1342381SN/A    /**
1352381SN/A     * Reconstruct the state of this object from a checkpoint.
1362381SN/A     * @param cp The checkpoint use.
1372657Ssaidi@eecs.umich.edu     * @param section The section name of this object
1382381SN/A     */
1392381SN/A    virtual void unserialize(Checkpoint *cp, const std::string &section);
1402381SN/A};
1412381SN/A
1422381SN/A#endif // __DEV_MALTA_HH__
1432381SN/A