Malta.py revision 9338
15222Sksewell@umich.edu# Copyright (c) 2007 The Regents of The University of Michigan
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265222Sksewell@umich.edu#
275222Sksewell@umich.edu# Authors: Korey Sewell
285222Sksewell@umich.edu
295222Sksewell@umich.edufrom m5.params import *
305222Sksewell@umich.edufrom m5.proxy import *
315481Snate@binkert.org
325481Snate@binkert.orgfrom BadDevice import BadDevice
335222Sksewell@umich.edufrom Device import BasicPioDevice
345481Snate@binkert.orgfrom Pci import PciConfigAll
355222Sksewell@umich.edufrom Platform import Platform
365222Sksewell@umich.edufrom Uart import Uart8250
375222Sksewell@umich.edu
385222Sksewell@umich.educlass MaltaCChip(BasicPioDevice):
395222Sksewell@umich.edu    type = 'MaltaCChip'
409338SAndreas.Sandberg@arm.com    cxx_header = "dev/mips/malta_cchip.hh"
415222Sksewell@umich.edu    malta = Param.Malta(Parent.any, "Malta")
425222Sksewell@umich.edu
435222Sksewell@umich.educlass MaltaIO(BasicPioDevice):
445222Sksewell@umich.edu    type = 'MaltaIO'
459338SAndreas.Sandberg@arm.com    cxx_header = "dev/mips/malta_io.hh"
466379Sgblack@eecs.umich.edu    time = Param.Time('01/01/2009',
475222Sksewell@umich.edu        "System time to use (0 for actual time, default is 1/1/06)")
486379Sgblack@eecs.umich.edu    year_is_bcd = Param.Bool(False,
496379Sgblack@eecs.umich.edu            "The RTC should interpret the year as a BCD value")
505222Sksewell@umich.edu    malta = Param.Malta(Parent.any, "Malta")
516379Sgblack@eecs.umich.edu    frequency = Param.Frequency('1024Hz', "frequency of interrupts")
525222Sksewell@umich.edu
535222Sksewell@umich.educlass MaltaPChip(BasicPioDevice):
545222Sksewell@umich.edu    type = 'MaltaPChip'
559338SAndreas.Sandberg@arm.com    cxx_header = "dev/mips/malta_pchip.hh"
565222Sksewell@umich.edu    malta = Param.Malta(Parent.any, "Malta")
575222Sksewell@umich.edu
585222Sksewell@umich.educlass Malta(Platform):
595222Sksewell@umich.edu    type = 'Malta'
609338SAndreas.Sandberg@arm.com    cxx_header = "dev/mips/malta.hh"
615222Sksewell@umich.edu    system = Param.System(Parent.any, "system")
625222Sksewell@umich.edu    cchip = MaltaCChip(pio_addr=0x801a0000000)
635222Sksewell@umich.edu    io = MaltaIO(pio_addr=0x801fc000000)
645222Sksewell@umich.edu    uart = Uart8250(pio_addr=0xBFD003F8)
655222Sksewell@umich.edu
665222Sksewell@umich.edu    # Attach I/O devices to specified bus object.  Can't do this
675222Sksewell@umich.edu    # earlier, since the bus object itself is typically defined at the
685222Sksewell@umich.edu    # System level.
695222Sksewell@umich.edu    def attachIO(self, bus):
708847Sandreas.hansson@arm.com        self.cchip.pio = bus.master
718847Sandreas.hansson@arm.com        self.io.pio = bus.master
728847Sandreas.hansson@arm.com        self.uart.pio = bus.master
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