isa_fake.cc revision 1817
111793Sbrandon.potter@amd.com/* 211793Sbrandon.potter@amd.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 311184Serfan.azarkhish@unibo.it * All rights reserved. 411184Serfan.azarkhish@unibo.it * 511184Serfan.azarkhish@unibo.it * Redistribution and use in source and binary forms, with or without 611184Serfan.azarkhish@unibo.it * modification, are permitted provided that the following conditions are 711184Serfan.azarkhish@unibo.it * met: redistributions of source code must retain the above copyright 811184Serfan.azarkhish@unibo.it * notice, this list of conditions and the following disclaimer; 911184Serfan.azarkhish@unibo.it * redistributions in binary form must reproduce the above copyright 1011184Serfan.azarkhish@unibo.it * notice, this list of conditions and the following disclaimer in the 1111184Serfan.azarkhish@unibo.it * documentation and/or other materials provided with the distribution; 1211184Serfan.azarkhish@unibo.it * neither the name of the copyright holders nor the names of its 1311184Serfan.azarkhish@unibo.it * contributors may be used to endorse or promote products derived from 1411184Serfan.azarkhish@unibo.it * this software without specific prior written permission. 1511184Serfan.azarkhish@unibo.it * 1611184Serfan.azarkhish@unibo.it * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711184Serfan.azarkhish@unibo.it * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811184Serfan.azarkhish@unibo.it * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911184Serfan.azarkhish@unibo.it * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011184Serfan.azarkhish@unibo.it * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111184Serfan.azarkhish@unibo.it * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211184Serfan.azarkhish@unibo.it * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311184Serfan.azarkhish@unibo.it * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411184Serfan.azarkhish@unibo.it * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511184Serfan.azarkhish@unibo.it * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611184Serfan.azarkhish@unibo.it * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711184Serfan.azarkhish@unibo.it */ 2811184Serfan.azarkhish@unibo.it 2911184Serfan.azarkhish@unibo.it/** @file 3011184Serfan.azarkhish@unibo.it * Isa Fake Device implementation 3111184Serfan.azarkhish@unibo.it */ 3211184Serfan.azarkhish@unibo.it 3311184Serfan.azarkhish@unibo.it#include <deque> 3411184Serfan.azarkhish@unibo.it#include <string> 3511184Serfan.azarkhish@unibo.it#include <vector> 3611184Serfan.azarkhish@unibo.it 3711184Serfan.azarkhish@unibo.it#include "base/trace.hh" 3811184Serfan.azarkhish@unibo.it#include "cpu/exec_context.hh" 3911184Serfan.azarkhish@unibo.it#include "dev/isa_fake.hh" 4011184Serfan.azarkhish@unibo.it#include "mem/bus/bus.hh" 4111184Serfan.azarkhish@unibo.it#include "mem/bus/pio_interface.hh" 4211184Serfan.azarkhish@unibo.it#include "mem/bus/pio_interface_impl.hh" 4311184Serfan.azarkhish@unibo.it#include "mem/functional/memory_control.hh" 4411184Serfan.azarkhish@unibo.it#include "sim/builder.hh" 4511184Serfan.azarkhish@unibo.it#include "sim/system.hh" 4611184Serfan.azarkhish@unibo.it 4711184Serfan.azarkhish@unibo.itusing namespace std; 4811184Serfan.azarkhish@unibo.it 4911184Serfan.azarkhish@unibo.itIsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, 5011184Serfan.azarkhish@unibo.it HierParams *hier, Bus *bus, Addr size) 5111184Serfan.azarkhish@unibo.it : PioDevice(name, NULL), addr(a) 5211184Serfan.azarkhish@unibo.it{ 5311184Serfan.azarkhish@unibo.it mmu->add_child(this, RangeSize(addr, size)); 5411184Serfan.azarkhish@unibo.it 5511184Serfan.azarkhish@unibo.it if (bus) { 5611184Serfan.azarkhish@unibo.it pioInterface = newPioInterface(name, hier, bus, this, 5711184Serfan.azarkhish@unibo.it &IsaFake::cacheAccess); 5811184Serfan.azarkhish@unibo.it pioInterface->addAddrRange(RangeSize(addr, size)); 5911184Serfan.azarkhish@unibo.it } 6011184Serfan.azarkhish@unibo.it} 6111184Serfan.azarkhish@unibo.it 6211184Serfan.azarkhish@unibo.itFault 6311184Serfan.azarkhish@unibo.itIsaFake::read(MemReqPtr &req, uint8_t *data) 6411184Serfan.azarkhish@unibo.it{ 6511184Serfan.azarkhish@unibo.it DPRINTF(Tsunami, "read va=%#x size=%d\n", 6611184Serfan.azarkhish@unibo.it req->vaddr, req->size); 6711184Serfan.azarkhish@unibo.it 6811184Serfan.azarkhish@unibo.it#if TRACING_ON 6911184Serfan.azarkhish@unibo.it Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; 7011184Serfan.azarkhish@unibo.it#endif 7111184Serfan.azarkhish@unibo.it 7211184Serfan.azarkhish@unibo.it switch (req->size) { 7311184Serfan.azarkhish@unibo.it 7411184Serfan.azarkhish@unibo.it case sizeof(uint64_t): 7511184Serfan.azarkhish@unibo.it *(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL; 7611184Serfan.azarkhish@unibo.it return No_Fault; 7711184Serfan.azarkhish@unibo.it case sizeof(uint32_t): 7811184Serfan.azarkhish@unibo.it *(uint32_t*)data = 0xFFFFFFFF; 7911184Serfan.azarkhish@unibo.it return No_Fault; 8011184Serfan.azarkhish@unibo.it case sizeof(uint16_t): 8111184Serfan.azarkhish@unibo.it *(uint16_t*)data = 0xFFFF; 8211184Serfan.azarkhish@unibo.it return No_Fault; 8311184Serfan.azarkhish@unibo.it case sizeof(uint8_t): 8411184Serfan.azarkhish@unibo.it *(uint8_t*)data = 0xFF; 8511284Sandreas.hansson@arm.com return No_Fault; 8611184Serfan.azarkhish@unibo.it 8711184Serfan.azarkhish@unibo.it default: 8811184Serfan.azarkhish@unibo.it panic("invalid access size(?) for PCI configspace!\n"); 8911184Serfan.azarkhish@unibo.it } 9011184Serfan.azarkhish@unibo.it DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size); 9111184Serfan.azarkhish@unibo.it 9211184Serfan.azarkhish@unibo.it return No_Fault; 9311184Serfan.azarkhish@unibo.it} 9411184Serfan.azarkhish@unibo.it 9511184Serfan.azarkhish@unibo.itFault 9611184Serfan.azarkhish@unibo.itIsaFake::write(MemReqPtr &req, const uint8_t *data) 9711184Serfan.azarkhish@unibo.it{ 9811184Serfan.azarkhish@unibo.it DPRINTF(Tsunami, "write - va=%#x size=%d \n", 9911184Serfan.azarkhish@unibo.it req->vaddr, req->size); 10011184Serfan.azarkhish@unibo.it 10111184Serfan.azarkhish@unibo.it //:Addr daddr = (req->paddr & addr_mask) >> 6; 10211184Serfan.azarkhish@unibo.it 10311184Serfan.azarkhish@unibo.it return No_Fault; 10411184Serfan.azarkhish@unibo.it} 10511184Serfan.azarkhish@unibo.it 10611184Serfan.azarkhish@unibo.itTick 10711184Serfan.azarkhish@unibo.itIsaFake::cacheAccess(MemReqPtr &req) 10811184Serfan.azarkhish@unibo.it{ 10911184Serfan.azarkhish@unibo.it return curTick; 11011184Serfan.azarkhish@unibo.it} 11111184Serfan.azarkhish@unibo.it 11211184Serfan.azarkhish@unibo.itBEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake) 11311184Serfan.azarkhish@unibo.it 11411184Serfan.azarkhish@unibo.it SimObjectParam<MemoryController *> mmu; 11511184Serfan.azarkhish@unibo.it Param<Addr> addr; 11611184Serfan.azarkhish@unibo.it SimObjectParam<Bus*> io_bus; 11711184Serfan.azarkhish@unibo.it Param<Tick> pio_latency; 11811184Serfan.azarkhish@unibo.it SimObjectParam<HierParams *> hier; 119 Param<Addr> size; 120 121END_DECLARE_SIM_OBJECT_PARAMS(IsaFake) 122 123BEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake) 124 125 INIT_PARAM(mmu, "Memory Controller"), 126 INIT_PARAM(addr, "Device Address"), 127 INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), 128 INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), 129 INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams), 130 INIT_PARAM_DFLT(size, "Size of address range", 0x8) 131 132END_INIT_SIM_OBJECT_PARAMS(IsaFake) 133 134CREATE_SIM_OBJECT(IsaFake) 135{ 136 return new IsaFake(getInstanceName(), addr, mmu, hier, io_bus, size); 137} 138 139REGISTER_SIM_OBJECT("IsaFake", IsaFake) 140