isa_fake.cc revision 1817
11689SN/A/* 22325SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 292756Sksewell@umich.edu/** @file 301689SN/A * Isa Fake Device implementation 311689SN/A */ 321858SN/A 332733Sktlim@umich.edu#include <deque> 341858SN/A#include <string> 351858SN/A#include <vector> 361060SN/A 371060SN/A#include "base/trace.hh" 381060SN/A#include "cpu/exec_context.hh" 391060SN/A#include "dev/isa_fake.hh" 401060SN/A#include "mem/bus/bus.hh" 412325SN/A#include "mem/bus/pio_interface.hh" 422683Sktlim@umich.edu#include "mem/bus/pio_interface_impl.hh" 432680Sktlim@umich.edu#include "mem/functional/memory_control.hh" 442817Sksewell@umich.edu#include "sim/builder.hh" 451717SN/A#include "sim/system.hh" 461060SN/A 472325SN/Ausing namespace std; 482292SN/A 492292SN/AIsaFake::IsaFake(const string &name, Addr a, MemoryController *mmu, 502794Sktlim@umich.edu HierParams *hier, Bus *bus, Addr size) 512794Sktlim@umich.edu : PioDevice(name, NULL), addr(a) 522794Sktlim@umich.edu{ 532794Sktlim@umich.edu mmu->add_child(this, RangeSize(addr, size)); 541060SN/A 552669Sktlim@umich.edu if (bus) { 561060SN/A pioInterface = newPioInterface(name, hier, bus, this, 572733Sktlim@umich.edu &IsaFake::cacheAccess); 582292SN/A pioInterface->addAddrRange(RangeSize(addr, size)); 591060SN/A } 601060SN/A} 611060SN/A 622292SN/AFault 632733Sktlim@umich.eduIsaFake::read(MemReqPtr &req, uint8_t *data) 642292SN/A{ 652292SN/A DPRINTF(Tsunami, "read va=%#x size=%d\n", 662292SN/A req->vaddr, req->size); 672292SN/A 681060SN/A#if TRACING_ON 691755SN/A Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6; 701060SN/A#endif 711060SN/A 721060SN/A switch (req->size) { 731060SN/A 741060SN/A case sizeof(uint64_t): 751060SN/A *(uint64_t*)data = 0xFFFFFFFFFFFFFFFFULL; 761755SN/A return No_Fault; 771060SN/A case sizeof(uint32_t): 781060SN/A *(uint32_t*)data = 0xFFFFFFFF; 791060SN/A return No_Fault; 801060SN/A case sizeof(uint16_t): 811060SN/A *(uint16_t*)data = 0xFFFF; 821060SN/A return No_Fault; 831755SN/A case sizeof(uint8_t): 841060SN/A *(uint8_t*)data = 0xFF; 851755SN/A return No_Fault; 861060SN/A 871060SN/A default: 881060SN/A panic("invalid access size(?) for PCI configspace!\n"); 892829Sksewell@umich.edu } 902829Sksewell@umich.edu DPRINTFN("Isa FakeSMC ERROR: read daddr=%#x size=%d\n", daddr, req->size); 912829Sksewell@umich.edu 922829Sksewell@umich.edu return No_Fault; 932829Sksewell@umich.edu} 942829Sksewell@umich.edu 952829Sksewell@umich.eduFault 962829Sksewell@umich.eduIsaFake::write(MemReqPtr &req, const uint8_t *data) 972829Sksewell@umich.edu{ 982829Sksewell@umich.edu DPRINTF(Tsunami, "write - va=%#x size=%d \n", 992829Sksewell@umich.edu req->vaddr, req->size); 1002829Sksewell@umich.edu 1012829Sksewell@umich.edu //:Addr daddr = (req->paddr & addr_mask) >> 6; 1022829Sksewell@umich.edu 1032829Sksewell@umich.edu return No_Fault; 1042829Sksewell@umich.edu} 1052829Sksewell@umich.edu 1062829Sksewell@umich.eduTick 1072829Sksewell@umich.eduIsaFake::cacheAccess(MemReqPtr &req) 1082829Sksewell@umich.edu{ 1092829Sksewell@umich.edu return curTick; 1102829Sksewell@umich.edu} 1112829Sksewell@umich.edu 1122829Sksewell@umich.eduBEGIN_DECLARE_SIM_OBJECT_PARAMS(IsaFake) 1132829Sksewell@umich.edu 1142829Sksewell@umich.edu SimObjectParam<MemoryController *> mmu; 1152829Sksewell@umich.edu Param<Addr> addr; 1162829Sksewell@umich.edu SimObjectParam<Bus*> io_bus; 1172829Sksewell@umich.edu Param<Tick> pio_latency; 1182875Sksewell@umich.edu SimObjectParam<HierParams *> hier; 1192875Sksewell@umich.edu Param<Addr> size; 1202875Sksewell@umich.edu 1212875Sksewell@umich.eduEND_DECLARE_SIM_OBJECT_PARAMS(IsaFake) 1222875Sksewell@umich.edu 1232875Sksewell@umich.eduBEGIN_INIT_SIM_OBJECT_PARAMS(IsaFake) 1242875Sksewell@umich.edu 1252875Sksewell@umich.edu INIT_PARAM(mmu, "Memory Controller"), 1262875Sksewell@umich.edu INIT_PARAM(addr, "Device Address"), 1272875Sksewell@umich.edu INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL), 1282875Sksewell@umich.edu INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000), 1292875Sksewell@umich.edu INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams), 1302875Sksewell@umich.edu INIT_PARAM_DFLT(size, "Size of address range", 0x8) 1312875Sksewell@umich.edu 1322875Sksewell@umich.eduEND_INIT_SIM_OBJECT_PARAMS(IsaFake) 1332875Sksewell@umich.edu 1342875Sksewell@umich.eduCREATE_SIM_OBJECT(IsaFake) 1352875Sksewell@umich.edu{ 1362875Sksewell@umich.edu return new IsaFake(getInstanceName(), addr, mmu, hier, io_bus, size); 1372875Sksewell@umich.edu} 1382875Sksewell@umich.edu 1392875Sksewell@umich.eduREGISTER_SIM_OBJECT("IsaFake", IsaFake) 1402875Sksewell@umich.edu