1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Peter Enns
38 */
39
40
41/** @file
42 * Implementiation of an i2c bus
43 */
44
45#ifndef __DEV_I2C_BUS_HH__
46#define __DEV_I2C_BUS_HH__
47
48#include <map>
49
50#include "dev/io_device.hh"
51#include "params/I2CBus.hh"
52
53class I2CDevice;
54
55class I2CBus : public BasicPioDevice
56{
57  protected:
58
59    enum I2CState {
60        IDLE,
61        RECEIVING_ADDR,
62        RECEIVING_DATA,
63        SENDING_DATA,
64    };
65
66    /**
67     * Read [and Set] serial control bits:
68     * Bit [0] is SCL
69     * Bit [1] is SDA
70     *
71     * http://infocenter.arm.com/help/topic/com.arm.doc.dui0440b/Bbajdjeg.html
72     */
73    static const int SB_CONTROLS = 0x0;
74    /** Clear control bits. Analogous to SB_CONTROLS */
75    static const int SB_CONTROLC = 0x4;
76
77    /** I2C clock wire (0, 1). */
78    uint8_t scl;
79    /** I2C data wire (0, 1) */
80    uint8_t sda;
81
82    /**
83     * State used by I2CBus::write to determine what stage of an i2c
84     * transmission it is currently in.
85     */
86    enum I2CState state;
87
88    /**
89     * Order of the bit of the current message that is being sent or
90     * received (0 - 7).
91     */
92    int currBit;
93
94    /**
95     * Key used to access a device in the slave devices map. This
96     * is the same address that is specified in kernel board
97     * initialization code (e.g., arch/arm/mach-realview/core.c).
98     */
99    uint8_t i2cAddr;
100
101    /** 8-bit buffer used to send and receive messages bit by bit. */
102    uint8_t message;
103
104    /**
105     * All the slave i2c devices that are connected to this
106     * bus. Each device has an address that points to the actual
107     * device.
108     */
109    std::map<uint8_t, I2CDevice*> devices;
110
111    /**
112     * Update data (sda) and clock (scl) to match any transitions
113     * specified by pkt.
114     *
115     * @param pkt memory request packet
116     */
117    void updateSignals(PacketPtr pkt);
118
119    /**
120     * Clock set check
121     *
122     * @param pkt memory request packet
123     * @return true if pkt indicates that scl transition from 0 to 1
124     */
125    bool isClockSet(PacketPtr pkt) const;
126
127    /**
128     * i2c start signal check
129     *
130     * @param pkt memory request packet
131     * @return true if pkt indicates a new transmission
132     */
133    bool isStart(PacketPtr pkt) const;
134
135    /**
136     * i2c end signal check
137     *
138     * @param pkt memory request packet
139     * @return true if pkt indicates stopping the current transmission
140     */
141    bool isEnd(PacketPtr pkt) const;
142
143  public:
144
145    I2CBus(const I2CBusParams* p);
146
147    Tick read(PacketPtr pkt) override;
148    Tick write(PacketPtr pkt) override;
149
150    void serialize(CheckpointOut &cp) const override;
151    void unserialize(CheckpointIn &cp) override;
152};
153
154#endif // __DEV_I2C_BUS_HH__
155