dma_device.cc revision 9814:7ad2b0186a32
1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Nathan Binkert 42 * Andreas Hansson 43 */ 44 45#include "base/chunk_generator.hh" 46#include "debug/DMA.hh" 47#include "debug/Drain.hh" 48#include "dev/dma_device.hh" 49#include "sim/system.hh" 50 51DmaPort::DmaPort(MemObject *dev, System *s) 52 : MasterPort(dev->name() + ".dma", dev), device(dev), sendEvent(this), 53 sys(s), masterId(s->getMasterId(dev->name())), 54 pendingCount(0), drainManager(NULL), 55 inRetry(false) 56{ } 57 58void 59DmaPort::handleResp(PacketPtr pkt, Tick delay) 60{ 61 // should always see a response with a sender state 62 assert(pkt->isResponse()); 63 64 // get the DMA sender state 65 DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState); 66 assert(state); 67 68 DPRINTF(DMA, "Received response %s for addr: %#x size: %d nb: %d," \ 69 " tot: %d sched %d\n", 70 pkt->cmdString(), pkt->getAddr(), pkt->req->getSize(), 71 state->numBytes, state->totBytes, 72 state->completionEvent ? 73 state->completionEvent->scheduled() : 0); 74 75 assert(pendingCount != 0); 76 pendingCount--; 77 78 // update the number of bytes received based on the request rather 79 // than the packet as the latter could be rounded up to line sizes 80 state->numBytes += pkt->req->getSize(); 81 assert(state->totBytes >= state->numBytes); 82 83 // if we have reached the total number of bytes for this DMA 84 // request, then signal the completion and delete the sate 85 if (state->totBytes == state->numBytes) { 86 if (state->completionEvent) { 87 delay += state->delay; 88 device->schedule(state->completionEvent, curTick() + delay); 89 } 90 delete state; 91 } 92 93 // delete the request that we created and also the packet 94 delete pkt->req; 95 delete pkt; 96 97 // we might be drained at this point, if so signal the drain event 98 if (pendingCount == 0 && drainManager) { 99 drainManager->signalDrainDone(); 100 drainManager = NULL; 101 } 102} 103 104bool 105DmaPort::recvTimingResp(PacketPtr pkt) 106{ 107 // We shouldn't ever get a block in ownership state 108 assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 109 110 handleResp(pkt); 111 112 return true; 113} 114 115DmaDevice::DmaDevice(const Params *p) 116 : PioDevice(p), dmaPort(this, sys) 117{ } 118 119void 120DmaDevice::init() 121{ 122 if (!dmaPort.isConnected()) 123 panic("DMA port of %s not connected to anything!", name()); 124 PioDevice::init(); 125} 126 127unsigned int 128DmaDevice::drain(DrainManager *dm) 129{ 130 unsigned int count = pioPort.drain(dm) + dmaPort.drain(dm); 131 if (count) 132 setDrainState(Drainable::Draining); 133 else 134 setDrainState(Drainable::Drained); 135 return count; 136} 137 138unsigned int 139DmaPort::drain(DrainManager *dm) 140{ 141 if (pendingCount == 0) 142 return 0; 143 drainManager = dm; 144 DPRINTF(Drain, "DmaPort not drained\n"); 145 return 1; 146} 147 148void 149DmaPort::recvRetry() 150{ 151 assert(transmitList.size()); 152 trySendTimingReq(); 153} 154 155void 156DmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 157 uint8_t *data, Tick delay, Request::Flags flag) 158{ 159 // one DMA request sender state for every action, that is then 160 // split into many requests and packets based on the block size, 161 // i.e. cache line size 162 DmaReqState *reqState = new DmaReqState(event, size, delay); 163 164 DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size, 165 event ? event->scheduled() : -1); 166 for (ChunkGenerator gen(addr, size, sys->cacheLineSize()); 167 !gen.done(); gen.next()) { 168 Request *req = new Request(gen.addr(), gen.size(), flag, masterId); 169 PacketPtr pkt = new Packet(req, cmd); 170 171 // Increment the data pointer on a write 172 if (data) 173 pkt->dataStatic(data + gen.complete()); 174 175 pkt->senderState = reqState; 176 177 DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(), 178 gen.size()); 179 queueDma(pkt); 180 } 181 182 // in zero time also initiate the sending of the packets we have 183 // just created, for atomic this involves actually completing all 184 // the requests 185 sendDma(); 186} 187 188void 189DmaPort::queueDma(PacketPtr pkt) 190{ 191 transmitList.push_back(pkt); 192 193 // remember that we have another packet pending, this will only be 194 // decremented once a response comes back 195 pendingCount++; 196} 197 198void 199DmaPort::trySendTimingReq() 200{ 201 // send the first packet on the transmit list and schedule the 202 // following send if it is successful 203 PacketPtr pkt = transmitList.front(); 204 205 DPRINTF(DMA, "Trying to send %s addr %#x\n", pkt->cmdString(), 206 pkt->getAddr()); 207 208 inRetry = !sendTimingReq(pkt); 209 if (!inRetry) { 210 transmitList.pop_front(); 211 DPRINTF(DMA, "-- Done\n"); 212 // if there is more to do, then do so 213 if (!transmitList.empty()) 214 // this should ultimately wait for as many cycles as the 215 // device needs to send the packet, but currently the port 216 // does not have any known width so simply wait a single 217 // cycle 218 device->schedule(sendEvent, device->clockEdge(Cycles(1))); 219 } else { 220 DPRINTF(DMA, "-- Failed, waiting for retry\n"); 221 } 222 223 DPRINTF(DMA, "TransmitList: %d, inRetry: %d\n", 224 transmitList.size(), inRetry); 225} 226 227void 228DmaPort::sendDma() 229{ 230 // some kind of selcetion between access methods 231 // more work is going to have to be done to make 232 // switching actually work 233 assert(transmitList.size()); 234 235 if (sys->isTimingMode()) { 236 // if we are either waiting for a retry or are still waiting 237 // after sending the last packet, then do not proceed 238 if (inRetry || sendEvent.scheduled()) { 239 DPRINTF(DMA, "Can't send immediately, waiting to send\n"); 240 return; 241 } 242 243 trySendTimingReq(); 244 } else if (sys->isAtomicMode()) { 245 // send everything there is to send in zero time 246 while (!transmitList.empty()) { 247 PacketPtr pkt = transmitList.front(); 248 transmitList.pop_front(); 249 250 DPRINTF(DMA, "Sending DMA for addr: %#x size: %d\n", 251 pkt->req->getPaddr(), pkt->req->getSize()); 252 Tick lat = sendAtomic(pkt); 253 254 handleResp(pkt, lat); 255 } 256 } else 257 panic("Unknown memory mode."); 258} 259 260BaseMasterPort & 261DmaDevice::getMasterPort(const std::string &if_name, PortID idx) 262{ 263 if (if_name == "dma") { 264 return dmaPort; 265 } 266 return PioDevice::getMasterPort(if_name, idx); 267} 268