dma_device.cc revision 9294
1545SN/A/* 28948SN/A * Copyright (c) 2012 ARM Limited 38948SN/A * All rights reserved. 48948SN/A * 58948SN/A * The license below extends only to copyright in the software and shall 68948SN/A * not be construed as granting a license to any other intellectual 78948SN/A * property including but not limited to intellectual property relating 88948SN/A * to a hardware implementation of the functionality of the software 98948SN/A * licensed hereunder. You may use the software subject to the license 108948SN/A * terms below provided that you ensure that this notice is replicated 118948SN/A * unmodified and in its entirety in all distributions of the software, 128948SN/A * modified or unmodified, in source code or in binary form. 138948SN/A * 142512SN/A * Copyright (c) 2006 The Regents of The University of Michigan 15545SN/A * All rights reserved. 16545SN/A * 17545SN/A * Redistribution and use in source and binary forms, with or without 18545SN/A * modification, are permitted provided that the following conditions are 19545SN/A * met: redistributions of source code must retain the above copyright 20545SN/A * notice, this list of conditions and the following disclaimer; 21545SN/A * redistributions in binary form must reproduce the above copyright 22545SN/A * notice, this list of conditions and the following disclaimer in the 23545SN/A * documentation and/or other materials provided with the distribution; 24545SN/A * neither the name of the copyright holders nor the names of its 25545SN/A * contributors may be used to endorse or promote products derived from 26545SN/A * this software without specific prior written permission. 27545SN/A * 28545SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29545SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30545SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31545SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32545SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33545SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34545SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35545SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36545SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37545SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38545SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ali Saidi 412665SN/A * Nathan Binkert 429166Sandreas.hansson@arm.com * Andreas Hansson 43545SN/A */ 44545SN/A 453090SN/A#include "base/chunk_generator.hh" 468232SN/A#include "debug/DMA.hh" 479152Satgutier@umich.edu#include "debug/Drain.hh" 489016Sandreas.hansson@arm.com#include "dev/dma_device.hh" 492901SN/A#include "sim/system.hh" 50545SN/A 519165Sandreas.hansson@arm.comDmaPort::DmaPort(MemObject *dev, System *s) 529095Sandreas.hansson@arm.com : MasterPort(dev->name() + ".dma", dev), device(dev), sys(s), 538832SN/A masterId(s->getMasterId(dev->name())), 549133Satgutier@umich.edu pendingCount(0), drainEvent(NULL), 559165Sandreas.hansson@arm.com inRetry(false) 562489SN/A{ } 572489SN/A 589166Sandreas.hansson@arm.comvoid 599166Sandreas.hansson@arm.comDmaPort::handleResp(PacketPtr pkt, Tick delay) 609166Sandreas.hansson@arm.com{ 619166Sandreas.hansson@arm.com // should always see a response with a sender state 629166Sandreas.hansson@arm.com assert(pkt->isResponse()); 639166Sandreas.hansson@arm.com 649166Sandreas.hansson@arm.com // get the DMA sender state 659166Sandreas.hansson@arm.com DmaReqState *state = dynamic_cast<DmaReqState*>(pkt->senderState); 669166Sandreas.hansson@arm.com assert(state); 679166Sandreas.hansson@arm.com 689166Sandreas.hansson@arm.com DPRINTF(DMA, "Received response %s for addr: %#x size: %d nb: %d," \ 699166Sandreas.hansson@arm.com " tot: %d sched %d\n", 709166Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->req->getSize(), 719166Sandreas.hansson@arm.com state->numBytes, state->totBytes, 729166Sandreas.hansson@arm.com state->completionEvent ? 739166Sandreas.hansson@arm.com state->completionEvent->scheduled() : 0); 749166Sandreas.hansson@arm.com 759166Sandreas.hansson@arm.com assert(pendingCount != 0); 769166Sandreas.hansson@arm.com pendingCount--; 779166Sandreas.hansson@arm.com 789166Sandreas.hansson@arm.com // update the number of bytes received based on the request rather 799166Sandreas.hansson@arm.com // than the packet as the latter could be rounded up to line sizes 809166Sandreas.hansson@arm.com state->numBytes += pkt->req->getSize(); 819166Sandreas.hansson@arm.com assert(state->totBytes >= state->numBytes); 829166Sandreas.hansson@arm.com 839166Sandreas.hansson@arm.com // if we have reached the total number of bytes for this DMA 849166Sandreas.hansson@arm.com // request, then signal the completion and delete the sate 859166Sandreas.hansson@arm.com if (state->totBytes == state->numBytes) { 869166Sandreas.hansson@arm.com if (state->completionEvent) { 879166Sandreas.hansson@arm.com delay += state->delay; 889166Sandreas.hansson@arm.com if (delay) 899166Sandreas.hansson@arm.com device->schedule(state->completionEvent, curTick() + delay); 909166Sandreas.hansson@arm.com else 919166Sandreas.hansson@arm.com state->completionEvent->process(); 929166Sandreas.hansson@arm.com } 939166Sandreas.hansson@arm.com delete state; 949166Sandreas.hansson@arm.com } 959166Sandreas.hansson@arm.com 969166Sandreas.hansson@arm.com // delete the request that we created and also the packet 979166Sandreas.hansson@arm.com delete pkt->req; 989166Sandreas.hansson@arm.com delete pkt; 999166Sandreas.hansson@arm.com 1009166Sandreas.hansson@arm.com // we might be drained at this point, if so signal the drain event 1019166Sandreas.hansson@arm.com if (pendingCount == 0 && drainEvent) { 1029166Sandreas.hansson@arm.com drainEvent->process(); 1039166Sandreas.hansson@arm.com drainEvent = NULL; 1049166Sandreas.hansson@arm.com } 1059166Sandreas.hansson@arm.com} 1069166Sandreas.hansson@arm.com 1072489SN/Abool 1088975SN/ADmaPort::recvTimingResp(PacketPtr pkt) 1092384SN/A{ 1109166Sandreas.hansson@arm.com // We shouldn't ever get a block in ownership state 1119166Sandreas.hansson@arm.com assert(!(pkt->memInhibitAsserted() && !pkt->sharedAsserted())); 1124435SN/A 1139166Sandreas.hansson@arm.com handleResp(pkt); 1142569SN/A 1152657SN/A return true; 1162384SN/A} 117679SN/A 1184762SN/ADmaDevice::DmaDevice(const Params *p) 1199165Sandreas.hansson@arm.com : PioDevice(p), dmaPort(this, sys) 1202565SN/A{ } 1212384SN/A 1228851SN/Avoid 1238851SN/ADmaDevice::init() 1248851SN/A{ 1258851SN/A if (!dmaPort.isConnected()) 1268851SN/A panic("DMA port of %s not connected to anything!", name()); 1278851SN/A PioDevice::init(); 1288851SN/A} 1298851SN/A 1302901SN/Aunsigned int 1312901SN/ADmaDevice::drain(Event *de) 1322901SN/A{ 1339166Sandreas.hansson@arm.com unsigned int count = pioPort.drain(de) + dmaPort.drain(de); 1342901SN/A if (count) 1352901SN/A changeState(Draining); 1362901SN/A else 1372901SN/A changeState(Drained); 1382901SN/A return count; 1392901SN/A} 1402901SN/A 1412901SN/Aunsigned int 1422901SN/ADmaPort::drain(Event *de) 1432901SN/A{ 1449166Sandreas.hansson@arm.com if (pendingCount == 0) 1452901SN/A return 0; 1462901SN/A drainEvent = de; 1479152Satgutier@umich.edu DPRINTF(Drain, "DmaPort not drained\n"); 1482901SN/A return 1; 1492901SN/A} 1502901SN/A 1512384SN/Avoid 1522489SN/ADmaPort::recvRetry() 1532489SN/A{ 1544435SN/A assert(transmitList.size()); 1552659SN/A bool result = true; 1564435SN/A do { 1575539SN/A PacketPtr pkt = transmitList.front(); 1584739SN/A DPRINTF(DMA, "Retry on %s addr %#x\n", 1594739SN/A pkt->cmdString(), pkt->getAddr()); 1608975SN/A result = sendTimingReq(pkt); 1612659SN/A if (result) { 1622659SN/A DPRINTF(DMA, "-- Done\n"); 1632659SN/A transmitList.pop_front(); 1644435SN/A inRetry = false; 1652659SN/A } else { 1664435SN/A inRetry = true; 1672659SN/A DPRINTF(DMA, "-- Failed, queued\n"); 1682659SN/A } 1699165Sandreas.hansson@arm.com } while (result && transmitList.size()); 1704435SN/A 1719165Sandreas.hansson@arm.com DPRINTF(DMA, "TransmitList: %d, inRetry: %d\n", 1729165Sandreas.hansson@arm.com transmitList.size(), inRetry); 1732489SN/A} 1742641SN/A 1752489SN/Avoid 1762641SN/ADmaPort::dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, 1777607SN/A uint8_t *data, Tick delay, Request::Flags flag) 1782384SN/A{ 1799166Sandreas.hansson@arm.com // one DMA request sender state for every action, that is then 1809166Sandreas.hansson@arm.com // split into many requests and packets based on the block size, 1819166Sandreas.hansson@arm.com // i.e. cache line size 1829016Sandreas.hansson@arm.com DmaReqState *reqState = new DmaReqState(event, size, delay); 1832384SN/A 1844451SN/A DPRINTF(DMA, "Starting DMA for addr: %#x size: %d sched: %d\n", addr, size, 1859166Sandreas.hansson@arm.com event ? event->scheduled() : -1); 1862406SN/A for (ChunkGenerator gen(addr, size, peerBlockSize()); 1872406SN/A !gen.done(); gen.next()) { 1889166Sandreas.hansson@arm.com Request *req = new Request(gen.addr(), gen.size(), flag, masterId); 1899166Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, cmd); 1902641SN/A 1919166Sandreas.hansson@arm.com // Increment the data pointer on a write 1929166Sandreas.hansson@arm.com if (data) 1939166Sandreas.hansson@arm.com pkt->dataStatic(data + gen.complete()); 1942641SN/A 1959166Sandreas.hansson@arm.com pkt->senderState = reqState; 1962641SN/A 1979166Sandreas.hansson@arm.com DPRINTF(DMA, "--Queuing DMA for addr: %#x size: %d\n", gen.addr(), 1989166Sandreas.hansson@arm.com gen.size()); 1999166Sandreas.hansson@arm.com queueDma(pkt); 2002384SN/A } 2012384SN/A} 2022384SN/A 2034435SN/Avoid 2049166Sandreas.hansson@arm.comDmaPort::queueDma(PacketPtr pkt) 2054435SN/A{ 2069166Sandreas.hansson@arm.com transmitList.push_back(pkt); 2074435SN/A 2089166Sandreas.hansson@arm.com // remember that we have another packet pending, this will only be 2099166Sandreas.hansson@arm.com // decremented once a response comes back 2109166Sandreas.hansson@arm.com pendingCount++; 2119166Sandreas.hansson@arm.com 2124435SN/A sendDma(); 2134435SN/A} 2144435SN/A 2152384SN/Avoid 2164435SN/ADmaPort::sendDma() 2172384SN/A{ 2189166Sandreas.hansson@arm.com // some kind of selcetion between access methods 2192901SN/A // more work is going to have to be done to make 2202901SN/A // switching actually work 2214435SN/A assert(transmitList.size()); 2224435SN/A PacketPtr pkt = transmitList.front(); 2232902SN/A 2244762SN/A Enums::MemoryMode state = sys->getMemoryMode(); 2254762SN/A if (state == Enums::timing) { 2269165Sandreas.hansson@arm.com if (inRetry) { 2279165Sandreas.hansson@arm.com DPRINTF(DMA, "Can't send immediately, waiting for retry\n"); 2284435SN/A return; 2294435SN/A } 2304435SN/A 2314739SN/A DPRINTF(DMA, "Attempting to send %s addr %#x\n", 2324739SN/A pkt->cmdString(), pkt->getAddr()); 2334435SN/A 2344435SN/A bool result; 2354435SN/A do { 2368975SN/A result = sendTimingReq(pkt); 2374435SN/A if (result) { 2384435SN/A transmitList.pop_front(); 2394435SN/A DPRINTF(DMA, "-- Done\n"); 2404435SN/A } else { 2414435SN/A inRetry = true; 2424435SN/A DPRINTF(DMA, "-- Failed: queued\n"); 2434435SN/A } 2449165Sandreas.hansson@arm.com } while (result && transmitList.size()); 2454762SN/A } else if (state == Enums::atomic) { 2464435SN/A transmitList.pop_front(); 2474435SN/A 2489166Sandreas.hansson@arm.com DPRINTF(DMA, "Sending DMA for addr: %#x size: %d\n", 2494451SN/A pkt->req->getPaddr(), pkt->req->getSize()); 2509166Sandreas.hansson@arm.com Tick lat = sendAtomic(pkt); 2512384SN/A 2529166Sandreas.hansson@arm.com handleResp(pkt, lat); 2539166Sandreas.hansson@arm.com } else 2549166Sandreas.hansson@arm.com panic("Unknown memory mode."); 255545SN/A} 2568598SN/A 2579294Sandreas.hansson@arm.comBaseMasterPort & 2589294Sandreas.hansson@arm.comDmaDevice::getMasterPort(const std::string &if_name, PortID idx) 2598598SN/A{ 2608598SN/A if (if_name == "dma") { 2618922SN/A return dmaPort; 2628598SN/A } 2638922SN/A return PioDevice::getMasterPort(if_name, idx); 2648598SN/A} 265