pl011.hh revision 9806:3f262c18ad5d 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementiation of a PL011 UART
46 */
47
48#ifndef __DEV_ARM_PL011_H__
49#define __DEV_ARM_PL011_H__
50
51#include "base/bitfield.hh"
52#include "base/bitunion.hh"
53#include "dev/arm/amba_device.hh"
54#include "dev/io_device.hh"
55#include "dev/uart.hh"
56#include "params/Pl011.hh"
57
58class BaseGic;
59
60class Pl011 : public Uart, public AmbaDevice
61{
62  protected:
63    static const uint64_t AMBA_ID = ULL(0xb105f00d00341011);
64    static const int UART_DR = 0x000;
65    static const int UART_FR = 0x018;
66    static const int UART_FR_CTS  = 0x001;
67    static const int UART_FR_TXFE = 0x080;
68    static const int UART_FR_RXFE = 0x010;
69    static const int UART_IBRD = 0x024;
70    static const int UART_FBRD = 0x028;
71    static const int UART_LCRH = 0x02C;
72    static const int UART_CR   = 0x030;
73    static const int UART_IFLS = 0x034;
74    static const int UART_IMSC = 0x038;
75    static const int UART_RIS  = 0x03C;
76    static const int UART_MIS  = 0x040;
77    static const int UART_ICR  = 0x044;
78
79    uint16_t control;
80
81    /** fractional baud rate divisor. Not used for anything but reporting
82     * written value */
83    uint16_t fbrd;
84
85    /** integer baud rate divisor. Not used for anything but reporting
86     * written value */
87    uint16_t ibrd;
88
89    /** Line control register. Not used for anything but reporting
90     * written value */
91    uint16_t lcrh;
92
93    /** interrupt fifo level register. Not used for anything but reporting
94     * written value */
95    uint16_t ifls;
96
97    BitUnion16(INTREG)
98        Bitfield<0> rimim;
99        Bitfield<1> ctsmim;
100        Bitfield<2> dcdmim;
101        Bitfield<3> dsrmim;
102        Bitfield<4> rxim;
103        Bitfield<5> txim;
104        Bitfield<6> rtim;
105        Bitfield<7> feim;
106        Bitfield<8> peim;
107        Bitfield<9> beim;
108        Bitfield<10> oeim;
109        Bitfield<15,11> rsvd;
110    EndBitUnion(INTREG)
111
112    /** interrupt mask register. */
113    INTREG imsc;
114
115    /** raw interrupt status register */
116    INTREG rawInt;
117
118    /** Masked interrupt status register */
119    INTREG maskInt;
120
121    /** Interrupt number to generate */
122    int intNum;
123
124    /** Gic to use for interrupting */
125    BaseGic *gic;
126
127    /** Should the simulation end on an EOT */
128    bool endOnEOT;
129
130    /** Delay before interrupting */
131    Tick intDelay;
132
133    /** Function to generate interrupt */
134    void generateInterrupt();
135
136    /** Wrapper to create an event out of the thing */
137    EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
138
139  public:
140   typedef Pl011Params Params;
141   const Params *
142    params() const
143    {
144        return dynamic_cast<const Params *>(_params);
145    }
146    Pl011(const Params *p);
147
148    virtual Tick read(PacketPtr pkt);
149    virtual Tick write(PacketPtr pkt);
150
151    /**
152     * Inform the uart that there is data available.
153     */
154    virtual void dataAvailable();
155
156
157    /**
158     * Return if we have an interrupt pending
159     * @return interrupt status
160     * @todo fix me when implementation improves
161     */
162    virtual bool intStatus() { return false; }
163
164    virtual void serialize(std::ostream &os);
165    virtual void unserialize(Checkpoint *cp, const std::string &section);
166
167};
168
169#endif //__DEV_ARM_PL011_H__
170