pl011.hh revision 9806:3f262c18ad5d
12440SN/A/* 22440SN/A * Copyright (c) 2010 ARM Limited 32440SN/A * All rights reserved 42440SN/A * 52440SN/A * The license below extends only to copyright in the software and shall 62440SN/A * not be construed as granting a license to any other intellectual 72440SN/A * property including but not limited to intellectual property relating 82440SN/A * to a hardware implementation of the functionality of the software 92440SN/A * licensed hereunder. You may use the software subject to the license 102440SN/A * terms below provided that you ensure that this notice is replicated 112440SN/A * unmodified and in its entirety in all distributions of the software, 122440SN/A * modified or unmodified, in source code or in binary form. 132440SN/A * 142440SN/A * Copyright (c) 2005 The Regents of The University of Michigan 152440SN/A * All rights reserved. 162440SN/A * 172440SN/A * Redistribution and use in source and binary forms, with or without 182440SN/A * modification, are permitted provided that the following conditions are 192440SN/A * met: redistributions of source code must retain the above copyright 202440SN/A * notice, this list of conditions and the following disclaimer; 212440SN/A * redistributions in binary form must reproduce the above copyright 222440SN/A * notice, this list of conditions and the following disclaimer in the 232440SN/A * documentation and/or other materials provided with the distribution; 242440SN/A * neither the name of the copyright holders nor the names of its 252440SN/A * contributors may be used to endorse or promote products derived from 262440SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372972Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382460SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392440SN/A * 403120Sgblack@eecs.umich.edu * Authors: Ali Saidi 412440SN/A */ 422440SN/A 432440SN/A 442440SN/A/** @file 454826Ssaidi@eecs.umich.edu * Implementiation of a PL011 UART 464826Ssaidi@eecs.umich.edu */ 473577Sgblack@eecs.umich.edu 483577Sgblack@eecs.umich.edu#ifndef __DEV_ARM_PL011_H__ 493577Sgblack@eecs.umich.edu#define __DEV_ARM_PL011_H__ 504172Ssaidi@eecs.umich.edu 513577Sgblack@eecs.umich.edu#include "base/bitfield.hh" 523577Sgblack@eecs.umich.edu#include "base/bitunion.hh" 532467SN/A#include "dev/arm/amba_device.hh" 542440SN/A#include "dev/io_device.hh" 552440SN/A#include "dev/uart.hh" 562440SN/A#include "params/Pl011.hh" 572440SN/A 582467SN/Aclass BaseGic; 592440SN/A 602440SN/Aclass Pl011 : public Uart, public AmbaDevice 612440SN/A{ 622440SN/A protected: 632467SN/A static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); 642440SN/A static const int UART_DR = 0x000; 652440SN/A static const int UART_FR = 0x018; 662440SN/A static const int UART_FR_CTS = 0x001; 672440SN/A static const int UART_FR_TXFE = 0x080; 682467SN/A static const int UART_FR_RXFE = 0x010; 692440SN/A static const int UART_IBRD = 0x024; 702440SN/A static const int UART_FBRD = 0x028; 712440SN/A static const int UART_LCRH = 0x02C; 722440SN/A static const int UART_CR = 0x030; 732467SN/A static const int UART_IFLS = 0x034; 742440SN/A static const int UART_IMSC = 0x038; 752440SN/A static const int UART_RIS = 0x03C; 762440SN/A static const int UART_MIS = 0x040; 772440SN/A static const int UART_ICR = 0x044; 782440SN/A 792467SN/A uint16_t control; 802440SN/A 812440SN/A /** fractional baud rate divisor. Not used for anything but reporting 822440SN/A * written value */ 832467SN/A uint16_t fbrd; 842440SN/A 852440SN/A /** integer baud rate divisor. Not used for anything but reporting 862440SN/A * written value */ 872440SN/A uint16_t ibrd; 882440SN/A 892467SN/A /** Line control register. Not used for anything but reporting 902440SN/A * written value */ 912440SN/A uint16_t lcrh; 922440SN/A 932467SN/A /** interrupt fifo level register. Not used for anything but reporting 942440SN/A * written value */ 952440SN/A uint16_t ifls; 962440SN/A 972440SN/A BitUnion16(INTREG) 982440SN/A Bitfield<0> rimim; 992440SN/A Bitfield<1> ctsmim; 1002440SN/A Bitfield<2> dcdmim; 1012440SN/A Bitfield<3> dsrmim; 1022440SN/A Bitfield<4> rxim; 1032440SN/A Bitfield<5> txim; 1042440SN/A Bitfield<6> rtim; 1052440SN/A Bitfield<7> feim; 1062440SN/A Bitfield<8> peim; 1072440SN/A Bitfield<9> beim; 1082680Sktlim@umich.edu Bitfield<10> oeim; 1092440SN/A Bitfield<15,11> rsvd; 1102680Sktlim@umich.edu EndBitUnion(INTREG) 1112680Sktlim@umich.edu 1122440SN/A /** interrupt mask register. */ 1133961Sgblack@eecs.umich.edu INTREG imsc; 1143961Sgblack@eecs.umich.edu 1154194Ssaidi@eecs.umich.edu /** raw interrupt status register */ 1164194Ssaidi@eecs.umich.edu INTREG rawInt; 1174194Ssaidi@eecs.umich.edu 1182440SN/A /** Masked interrupt status register */ 1192440SN/A INTREG maskInt; 1202440SN/A 1212440SN/A /** Interrupt number to generate */ 1222440SN/A int intNum; 1232440SN/A 1242440SN/A /** Gic to use for interrupting */ 1252467SN/A BaseGic *gic; 1262440SN/A 1272440SN/A /** Should the simulation end on an EOT */ 1282467SN/A bool endOnEOT; 1292440SN/A 1302440SN/A /** Delay before interrupting */ 1312467SN/A Tick intDelay; 1322467SN/A 1332440SN/A /** Function to generate interrupt */ 1342440SN/A void generateInterrupt(); 1352467SN/A 1362440SN/A /** Wrapper to create an event out of the thing */ 1372467SN/A EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent; 1382440SN/A 1392440SN/A public: 1402440SN/A typedef Pl011Params Params; 1412467SN/A const Params * 1422440SN/A params() const 1432440SN/A { 1442440SN/A return dynamic_cast<const Params *>(_params); 1452680Sktlim@umich.edu } 1462680Sktlim@umich.edu Pl011(const Params *p); 1472440SN/A 1482440SN/A virtual Tick read(PacketPtr pkt); 1492440SN/A virtual Tick write(PacketPtr pkt); 1502680Sktlim@umich.edu 1512440SN/A /** 1522680Sktlim@umich.edu * Inform the uart that there is data available. 1532680Sktlim@umich.edu */ 1542440SN/A virtual void dataAvailable(); 1552440SN/A 1562440SN/A 1572440SN/A /** 1582440SN/A * Return if we have an interrupt pending 159 * @return interrupt status 160 * @todo fix me when implementation improves 161 */ 162 virtual bool intStatus() { return false; } 163 164 virtual void serialize(std::ostream &os); 165 virtual void unserialize(Checkpoint *cp, const std::string §ion); 166 167}; 168 169#endif //__DEV_ARM_PL011_H__ 170