pl011.hh revision 7584 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43
44/** @file
45 * Implementiation of a PL011 UART
46 */
47
48#ifndef __DEV_ARM_PL011_H__
49#define __DEV_ARM_PL011_H__
50
51#include "base/range.hh"
52#include "dev/io_device.hh"
53#include "dev/uart.hh"
54#include "params/Pl011.hh"
55
56class Gic;
57
58class Pl011 : public Uart
59{
60  protected:
61    static const int UART_DR = 0x000;
62    static const int UART_FR = 0x018;
63    static const int UART_FR_CTS  = 0x001;
64    static const int UART_FR_TXFE = 0x080;
65    static const int UART_FR_RXFE = 0x010;
66    static const int UART_IBRD = 0x024;
67    static const int UART_FBRD = 0x028;
68    static const int UART_LCRH = 0x02C;
69    static const int UART_CR   = 0x030;
70    static const int UART_IFLS = 0x034;
71    static const int UART_IMSC = 0x038;
72    static const int UART_RIS  = 0x03C;
73    static const int UART_MIS  = 0x040;
74    static const int UART_ICR  = 0x044;
75    static const int UART_PER_ID0 = 0xFE0;
76    static const int UART_PER_ID1 = 0xFE4;
77    static const int UART_PER_ID2 = 0xFE8;
78    static const int UART_PER_ID3 = 0xFEC;
79    static const int UART_CEL_ID0 = 0xFF0;
80    static const int UART_CEL_ID1 = 0xFF4;
81    static const int UART_CEL_ID2 = 0xFF8;
82    static const int UART_CEL_ID3 = 0xFFC;
83
84    uint16_t control;
85
86    /** fractional baud rate divisor. Not used for anything but reporting
87     * written value */
88    uint16_t fbrd;
89
90    /** integer baud rate divisor. Not used for anything but reporting
91     * written value */
92    uint16_t ibrd;
93
94    /** Line control register. Not used for anything but reporting
95     * written value */
96    uint16_t lcrh;
97
98    /** interrupt fifo level register. Not used for anything but reporting
99     * written value */
100    uint16_t ifls;
101
102    BitUnion16(INTREG)
103        Bitfield<0> rimim;
104        Bitfield<1> ctsmim;
105        Bitfield<2> dcdmim;
106        Bitfield<3> dsrmim;
107        Bitfield<4> rxim;
108        Bitfield<5> txim;
109        Bitfield<6> rtim;
110        Bitfield<7> feim;
111        Bitfield<8> peim;
112        Bitfield<9> beim;
113        Bitfield<10> oeim;
114        Bitfield<15,11> rsvd;
115    EndBitUnion(INTREG)
116
117    /** interrupt mask register. */
118    INTREG imsc;
119
120    /** raw interrupt status register */
121    INTREG rawInt;
122
123    /** Masked interrupt status register */
124    INTREG maskInt;
125
126    /** Interrupt number to generate */
127    int intNum;
128
129    /** Gic to use for interrupting */
130    Gic *gic;
131
132    /** Should the simulation end on an EOT */
133    bool endOnEOT;
134
135    /** Delay before interrupting */
136    Tick intDelay;
137
138    /** Function to generate interrupt */
139    void generateInterrupt();
140
141    /** Wrapper to create an event out of the thing */
142    EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent;
143
144  public:
145   typedef Pl011Params Params;
146   const Params *
147    params() const
148    {
149        return dynamic_cast<const Params *>(_params);
150    }
151    Pl011(const Params *p);
152
153    virtual Tick read(PacketPtr pkt);
154    virtual Tick write(PacketPtr pkt);
155
156    /**
157     * Inform the uart that there is data available.
158     */
159    virtual void dataAvailable();
160
161
162    /**
163     * Return if we have an interrupt pending
164     * @return interrupt status
165     * @todo fix me when implementation improves
166     */
167    virtual bool intStatus() { return false; }
168
169    virtual void serialize(std::ostream &os);
170    virtual void unserialize(Checkpoint *cp, const std::string &section);
171
172};
173
174#endif //__DEV_ARM_PL011_H__
175