pl011.hh revision 9806
15245Sgblack@eecs.umich.edu/* 25245Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 35245Sgblack@eecs.umich.edu * All rights reserved 45245Sgblack@eecs.umich.edu * 57087Snate@binkert.org * The license below extends only to copyright in the software and shall 67087Snate@binkert.org * not be construed as granting a license to any other intellectual 77087Snate@binkert.org * property including but not limited to intellectual property relating 87087Snate@binkert.org * to a hardware implementation of the functionality of the software 97087Snate@binkert.org * licensed hereunder. You may use the software subject to the license 107087Snate@binkert.org * terms below provided that you ensure that this notice is replicated 117087Snate@binkert.org * unmodified and in its entirety in all distributions of the software, 127087Snate@binkert.org * modified or unmodified, in source code or in binary form. 135245Sgblack@eecs.umich.edu * 147087Snate@binkert.org * Copyright (c) 2005 The Regents of The University of Michigan 157087Snate@binkert.org * All rights reserved. 167087Snate@binkert.org * 177087Snate@binkert.org * Redistribution and use in source and binary forms, with or without 187087Snate@binkert.org * modification, are permitted provided that the following conditions are 197087Snate@binkert.org * met: redistributions of source code must retain the above copyright 207087Snate@binkert.org * notice, this list of conditions and the following disclaimer; 217087Snate@binkert.org * redistributions in binary form must reproduce the above copyright 225245Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237087Snate@binkert.org * documentation and/or other materials provided with the distribution; 245245Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 255245Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 265245Sgblack@eecs.umich.edu * this software without specific prior written permission. 275245Sgblack@eecs.umich.edu * 285245Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295245Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305245Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 315245Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 325245Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 335245Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 345245Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 355245Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 365245Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 375245Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 385245Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 395245Sgblack@eecs.umich.edu * 405245Sgblack@eecs.umich.edu * Authors: Ali Saidi 415245Sgblack@eecs.umich.edu */ 425245Sgblack@eecs.umich.edu 437912Shestness@cs.utexas.edu 445245Sgblack@eecs.umich.edu/** @file 455245Sgblack@eecs.umich.edu * Implementiation of a PL011 UART 465245Sgblack@eecs.umich.edu */ 475245Sgblack@eecs.umich.edu 485245Sgblack@eecs.umich.edu#ifndef __DEV_ARM_PL011_H__ 495245Sgblack@eecs.umich.edu#define __DEV_ARM_PL011_H__ 505245Sgblack@eecs.umich.edu 515245Sgblack@eecs.umich.edu#include "base/bitfield.hh" 525245Sgblack@eecs.umich.edu#include "base/bitunion.hh" 535245Sgblack@eecs.umich.edu#include "dev/arm/amba_device.hh" 545245Sgblack@eecs.umich.edu#include "dev/io_device.hh" 555245Sgblack@eecs.umich.edu#include "dev/uart.hh" 565245Sgblack@eecs.umich.edu#include "params/Pl011.hh" 575245Sgblack@eecs.umich.edu 585245Sgblack@eecs.umich.educlass BaseGic; 595245Sgblack@eecs.umich.edu 605245Sgblack@eecs.umich.educlass Pl011 : public Uart, public AmbaDevice 615245Sgblack@eecs.umich.edu{ 625245Sgblack@eecs.umich.edu protected: 635245Sgblack@eecs.umich.edu static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); 645245Sgblack@eecs.umich.edu static const int UART_DR = 0x000; 655245Sgblack@eecs.umich.edu static const int UART_FR = 0x018; 665245Sgblack@eecs.umich.edu static const int UART_FR_CTS = 0x001; 675245Sgblack@eecs.umich.edu static const int UART_FR_TXFE = 0x080; 685245Sgblack@eecs.umich.edu static const int UART_FR_RXFE = 0x010; 695245Sgblack@eecs.umich.edu static const int UART_IBRD = 0x024; 705895Sgblack@eecs.umich.edu static const int UART_FBRD = 0x028; 717912Shestness@cs.utexas.edu static const int UART_LCRH = 0x02C; 727912Shestness@cs.utexas.edu static const int UART_CR = 0x030; 735245Sgblack@eecs.umich.edu static const int UART_IFLS = 0x034; 747912Shestness@cs.utexas.edu static const int UART_IMSC = 0x038; 757912Shestness@cs.utexas.edu static const int UART_RIS = 0x03C; 767912Shestness@cs.utexas.edu static const int UART_MIS = 0x040; 777912Shestness@cs.utexas.edu static const int UART_ICR = 0x044; 787912Shestness@cs.utexas.edu 797912Shestness@cs.utexas.edu uint16_t control; 807912Shestness@cs.utexas.edu 817912Shestness@cs.utexas.edu /** fractional baud rate divisor. Not used for anything but reporting 827912Shestness@cs.utexas.edu * written value */ 837912Shestness@cs.utexas.edu uint16_t fbrd; 847912Shestness@cs.utexas.edu 857912Shestness@cs.utexas.edu /** integer baud rate divisor. Not used for anything but reporting 867912Shestness@cs.utexas.edu * written value */ 877912Shestness@cs.utexas.edu uint16_t ibrd; 887912Shestness@cs.utexas.edu 897912Shestness@cs.utexas.edu /** Line control register. Not used for anything but reporting 905895Sgblack@eecs.umich.edu * written value */ 917912Shestness@cs.utexas.edu uint16_t lcrh; 925245Sgblack@eecs.umich.edu 935245Sgblack@eecs.umich.edu /** interrupt fifo level register. Not used for anything but reporting 945245Sgblack@eecs.umich.edu * written value */ 955895Sgblack@eecs.umich.edu uint16_t ifls; 967912Shestness@cs.utexas.edu 977912Shestness@cs.utexas.edu BitUnion16(INTREG) 985245Sgblack@eecs.umich.edu Bitfield<0> rimim; 997912Shestness@cs.utexas.edu Bitfield<1> ctsmim; 1007912Shestness@cs.utexas.edu Bitfield<2> dcdmim; 1015245Sgblack@eecs.umich.edu Bitfield<3> dsrmim; 1025245Sgblack@eecs.umich.edu Bitfield<4> rxim; 1035245Sgblack@eecs.umich.edu Bitfield<5> txim; 1045245Sgblack@eecs.umich.edu Bitfield<6> rtim; 1055245Sgblack@eecs.umich.edu Bitfield<7> feim; 1065245Sgblack@eecs.umich.edu Bitfield<8> peim; 1075245Sgblack@eecs.umich.edu Bitfield<9> beim; 1085245Sgblack@eecs.umich.edu Bitfield<10> oeim; 1095245Sgblack@eecs.umich.edu Bitfield<15,11> rsvd; 1105245Sgblack@eecs.umich.edu EndBitUnion(INTREG) 1115245Sgblack@eecs.umich.edu 1127912Shestness@cs.utexas.edu /** interrupt mask register. */ 1137912Shestness@cs.utexas.edu INTREG imsc; 1147912Shestness@cs.utexas.edu 1157912Shestness@cs.utexas.edu /** raw interrupt status register */ 1167912Shestness@cs.utexas.edu INTREG rawInt; 1177912Shestness@cs.utexas.edu 1187912Shestness@cs.utexas.edu /** Masked interrupt status register */ 1197912Shestness@cs.utexas.edu INTREG maskInt; 1207912Shestness@cs.utexas.edu 1217912Shestness@cs.utexas.edu /** Interrupt number to generate */ 1227912Shestness@cs.utexas.edu int intNum; 1237912Shestness@cs.utexas.edu 1247912Shestness@cs.utexas.edu /** Gic to use for interrupting */ 1257912Shestness@cs.utexas.edu BaseGic *gic; 1267912Shestness@cs.utexas.edu 1275245Sgblack@eecs.umich.edu /** Should the simulation end on an EOT */ 1287912Shestness@cs.utexas.edu bool endOnEOT; 1297912Shestness@cs.utexas.edu 1307912Shestness@cs.utexas.edu /** Delay before interrupting */ 1317912Shestness@cs.utexas.edu Tick intDelay; 1327912Shestness@cs.utexas.edu 1337912Shestness@cs.utexas.edu /** Function to generate interrupt */ 1347912Shestness@cs.utexas.edu void generateInterrupt(); 1355895Sgblack@eecs.umich.edu 1365245Sgblack@eecs.umich.edu /** Wrapper to create an event out of the thing */ 1377912Shestness@cs.utexas.edu EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent; 1387912Shestness@cs.utexas.edu 1395245Sgblack@eecs.umich.edu public: 1405245Sgblack@eecs.umich.edu typedef Pl011Params Params; 1415245Sgblack@eecs.umich.edu const Params * 1425245Sgblack@eecs.umich.edu params() const 1435245Sgblack@eecs.umich.edu { 1445245Sgblack@eecs.umich.edu return dynamic_cast<const Params *>(_params); 1455245Sgblack@eecs.umich.edu } 1465245Sgblack@eecs.umich.edu Pl011(const Params *p); 1475245Sgblack@eecs.umich.edu 1485245Sgblack@eecs.umich.edu virtual Tick read(PacketPtr pkt); 1495245Sgblack@eecs.umich.edu virtual Tick write(PacketPtr pkt); 1505245Sgblack@eecs.umich.edu 1515245Sgblack@eecs.umich.edu /** 1525245Sgblack@eecs.umich.edu * Inform the uart that there is data available. 1535245Sgblack@eecs.umich.edu */ 1545245Sgblack@eecs.umich.edu virtual void dataAvailable(); 1555245Sgblack@eecs.umich.edu 1565245Sgblack@eecs.umich.edu 1575245Sgblack@eecs.umich.edu /** 1585245Sgblack@eecs.umich.edu * Return if we have an interrupt pending 1595245Sgblack@eecs.umich.edu * @return interrupt status 1605245Sgblack@eecs.umich.edu * @todo fix me when implementation improves 1615245Sgblack@eecs.umich.edu */ 1625245Sgblack@eecs.umich.edu virtual bool intStatus() { return false; } 1635245Sgblack@eecs.umich.edu 1645245Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 1655245Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 1665245Sgblack@eecs.umich.edu 1675245Sgblack@eecs.umich.edu}; 1685245Sgblack@eecs.umich.edu 1695245Sgblack@eecs.umich.edu#endif //__DEV_ARM_PL011_H__ 1705245Sgblack@eecs.umich.edu