pl011.hh revision 11168
17584SAli.Saidi@arm.com/* 210718SAndreas.Sandberg@ARM.com * Copyright (c) 2010-2015 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 157584SAli.Saidi@arm.com * All rights reserved. 167584SAli.Saidi@arm.com * 177584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 187584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 197584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 207584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 217584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 227584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 237584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 247584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 257584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 267584SAli.Saidi@arm.com * this software without specific prior written permission. 277584SAli.Saidi@arm.com * 287584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397584SAli.Saidi@arm.com * 407584SAli.Saidi@arm.com * Authors: Ali Saidi 4110718SAndreas.Sandberg@ARM.com * Andreas Sandberg 427584SAli.Saidi@arm.com */ 437584SAli.Saidi@arm.com 447584SAli.Saidi@arm.com 457584SAli.Saidi@arm.com/** @file 467584SAli.Saidi@arm.com * Implementiation of a PL011 UART 477584SAli.Saidi@arm.com */ 487584SAli.Saidi@arm.com 497584SAli.Saidi@arm.com#ifndef __DEV_ARM_PL011_H__ 507584SAli.Saidi@arm.com#define __DEV_ARM_PL011_H__ 517584SAli.Saidi@arm.com 529806Sstever@gmail.com#include "dev/arm/amba_device.hh" 537584SAli.Saidi@arm.com#include "dev/uart.hh" 547584SAli.Saidi@arm.com 559525SAndreas.Sandberg@ARM.comclass BaseGic; 5610718SAndreas.Sandberg@ARM.comstruct Pl011Params; 577584SAli.Saidi@arm.com 589806Sstever@gmail.comclass Pl011 : public Uart, public AmbaDevice 597584SAli.Saidi@arm.com{ 6010718SAndreas.Sandberg@ARM.com public: 6110718SAndreas.Sandberg@ARM.com Pl011(const Pl011Params *p); 6210718SAndreas.Sandberg@ARM.com 6311168Sandreas.hansson@arm.com void serialize(CheckpointOut &cp) const override; 6411168Sandreas.hansson@arm.com void unserialize(CheckpointIn &cp) override; 6510718SAndreas.Sandberg@ARM.com 6610718SAndreas.Sandberg@ARM.com public: // PioDevice 6711168Sandreas.hansson@arm.com Tick read(PacketPtr pkt) override; 6811168Sandreas.hansson@arm.com Tick write(PacketPtr pkt) override; 6910718SAndreas.Sandberg@ARM.com 7010718SAndreas.Sandberg@ARM.com public: // Uart 7111168Sandreas.hansson@arm.com void dataAvailable() override; 7210718SAndreas.Sandberg@ARM.com 7310718SAndreas.Sandberg@ARM.com 7410718SAndreas.Sandberg@ARM.com protected: // Interrupt handling 7510718SAndreas.Sandberg@ARM.com /** Function to generate interrupt */ 7610718SAndreas.Sandberg@ARM.com void generateInterrupt(); 7710718SAndreas.Sandberg@ARM.com 7810718SAndreas.Sandberg@ARM.com /** 7910718SAndreas.Sandberg@ARM.com * Assign new interrupt values and update interrupt signals 8010718SAndreas.Sandberg@ARM.com * 8110718SAndreas.Sandberg@ARM.com * A new interrupt is scheduled signalled if the set of unmasked 8210718SAndreas.Sandberg@ARM.com * interrupts goes empty to non-empty. Conversely, if the set of 8310718SAndreas.Sandberg@ARM.com * unmasked interrupts goes from non-empty to empty, the interrupt 8410718SAndreas.Sandberg@ARM.com * signal is cleared. 8510718SAndreas.Sandberg@ARM.com * 8610718SAndreas.Sandberg@ARM.com * @param ints New <i>raw</i> interrupt status 8710718SAndreas.Sandberg@ARM.com * @param mask New interrupt mask 8810718SAndreas.Sandberg@ARM.com */ 8910718SAndreas.Sandberg@ARM.com void setInterrupts(uint16_t ints, uint16_t mask); 9010718SAndreas.Sandberg@ARM.com /** 9110718SAndreas.Sandberg@ARM.com * Convenience function to update the interrupt mask 9210718SAndreas.Sandberg@ARM.com * 9310718SAndreas.Sandberg@ARM.com * @see setInterrupts 9410718SAndreas.Sandberg@ARM.com * @param mask New interrupt mask 9510718SAndreas.Sandberg@ARM.com */ 9610718SAndreas.Sandberg@ARM.com void setInterruptMask(uint16_t mask) { setInterrupts(rawInt, mask); } 9710718SAndreas.Sandberg@ARM.com /** 9810718SAndreas.Sandberg@ARM.com * Convenience function to raise a new interrupt 9910718SAndreas.Sandberg@ARM.com * 10010718SAndreas.Sandberg@ARM.com * @see setInterrupts 10110718SAndreas.Sandberg@ARM.com * @param ints Set of interrupts to raise 10210718SAndreas.Sandberg@ARM.com */ 10310718SAndreas.Sandberg@ARM.com void raiseInterrupts(uint16_t ints) { setInterrupts(rawInt | ints, imsc); } 10410718SAndreas.Sandberg@ARM.com /** 10510718SAndreas.Sandberg@ARM.com * Convenience function to clear interrupts 10610718SAndreas.Sandberg@ARM.com * 10710718SAndreas.Sandberg@ARM.com * @see setInterrupts 10810718SAndreas.Sandberg@ARM.com * @param ints Set of interrupts to clear 10910718SAndreas.Sandberg@ARM.com */ 11010718SAndreas.Sandberg@ARM.com void clearInterrupts(uint16_t ints) { setInterrupts(rawInt & ~ints, imsc); } 11110718SAndreas.Sandberg@ARM.com 11210718SAndreas.Sandberg@ARM.com /** Masked interrupt status register */ 11310718SAndreas.Sandberg@ARM.com const inline uint16_t maskInt() const { return rawInt & imsc; } 11410718SAndreas.Sandberg@ARM.com 11510718SAndreas.Sandberg@ARM.com /** Wrapper to create an event out of the thing */ 11610718SAndreas.Sandberg@ARM.com EventWrapper<Pl011, &Pl011::generateInterrupt> intEvent; 11710718SAndreas.Sandberg@ARM.com 11810718SAndreas.Sandberg@ARM.com protected: // Registers 1197587SAli.Saidi@arm.com static const uint64_t AMBA_ID = ULL(0xb105f00d00341011); 1207584SAli.Saidi@arm.com static const int UART_DR = 0x000; 1217584SAli.Saidi@arm.com static const int UART_FR = 0x018; 1227584SAli.Saidi@arm.com static const int UART_FR_CTS = 0x001; 1237584SAli.Saidi@arm.com static const int UART_FR_TXFE = 0x080; 1247584SAli.Saidi@arm.com static const int UART_FR_RXFE = 0x010; 1257584SAli.Saidi@arm.com static const int UART_IBRD = 0x024; 1267584SAli.Saidi@arm.com static const int UART_FBRD = 0x028; 1277584SAli.Saidi@arm.com static const int UART_LCRH = 0x02C; 1287584SAli.Saidi@arm.com static const int UART_CR = 0x030; 1297584SAli.Saidi@arm.com static const int UART_IFLS = 0x034; 1307584SAli.Saidi@arm.com static const int UART_IMSC = 0x038; 1317584SAli.Saidi@arm.com static const int UART_RIS = 0x03C; 1327584SAli.Saidi@arm.com static const int UART_MIS = 0x040; 1337584SAli.Saidi@arm.com static const int UART_ICR = 0x044; 1347584SAli.Saidi@arm.com 13510718SAndreas.Sandberg@ARM.com static const uint16_t UART_RIINTR = 1 << 0; 13610718SAndreas.Sandberg@ARM.com static const uint16_t UART_CTSINTR = 1 << 1; 13710718SAndreas.Sandberg@ARM.com static const uint16_t UART_CDCINTR = 1 << 2; 13810718SAndreas.Sandberg@ARM.com static const uint16_t UART_DSRINTR = 1 << 3; 13910718SAndreas.Sandberg@ARM.com static const uint16_t UART_RXINTR = 1 << 4; 14010718SAndreas.Sandberg@ARM.com static const uint16_t UART_TXINTR = 1 << 5; 14110718SAndreas.Sandberg@ARM.com static const uint16_t UART_RTINTR = 1 << 6; 14210718SAndreas.Sandberg@ARM.com static const uint16_t UART_FEINTR = 1 << 7; 14310718SAndreas.Sandberg@ARM.com static const uint16_t UART_PEINTR = 1 << 8; 14410718SAndreas.Sandberg@ARM.com static const uint16_t UART_BEINTR = 1 << 9; 14510718SAndreas.Sandberg@ARM.com static const uint16_t UART_OEINTR = 1 << 10; 14610718SAndreas.Sandberg@ARM.com 1477584SAli.Saidi@arm.com uint16_t control; 1487584SAli.Saidi@arm.com 1497584SAli.Saidi@arm.com /** fractional baud rate divisor. Not used for anything but reporting 1507584SAli.Saidi@arm.com * written value */ 1517584SAli.Saidi@arm.com uint16_t fbrd; 1527584SAli.Saidi@arm.com 1537584SAli.Saidi@arm.com /** integer baud rate divisor. Not used for anything but reporting 1547584SAli.Saidi@arm.com * written value */ 1557584SAli.Saidi@arm.com uint16_t ibrd; 1567584SAli.Saidi@arm.com 1577584SAli.Saidi@arm.com /** Line control register. Not used for anything but reporting 1587584SAli.Saidi@arm.com * written value */ 1597584SAli.Saidi@arm.com uint16_t lcrh; 1607584SAli.Saidi@arm.com 1617584SAli.Saidi@arm.com /** interrupt fifo level register. Not used for anything but reporting 1627584SAli.Saidi@arm.com * written value */ 1637584SAli.Saidi@arm.com uint16_t ifls; 1647584SAli.Saidi@arm.com 1657584SAli.Saidi@arm.com /** interrupt mask register. */ 16610718SAndreas.Sandberg@ARM.com uint16_t imsc; 1677584SAli.Saidi@arm.com 1687584SAli.Saidi@arm.com /** raw interrupt status register */ 16910718SAndreas.Sandberg@ARM.com uint16_t rawInt; 1707584SAli.Saidi@arm.com 17110718SAndreas.Sandberg@ARM.com protected: // Configuration 17210718SAndreas.Sandberg@ARM.com /** Gic to use for interrupting */ 17310718SAndreas.Sandberg@ARM.com BaseGic * const gic; 17410718SAndreas.Sandberg@ARM.com 17510718SAndreas.Sandberg@ARM.com /** Should the simulation end on an EOT */ 17610718SAndreas.Sandberg@ARM.com const bool endOnEOT; 1777584SAli.Saidi@arm.com 1787584SAli.Saidi@arm.com /** Interrupt number to generate */ 17910718SAndreas.Sandberg@ARM.com const int intNum; 1807584SAli.Saidi@arm.com 1817584SAli.Saidi@arm.com /** Delay before interrupting */ 18210718SAndreas.Sandberg@ARM.com const Tick intDelay; 1837584SAli.Saidi@arm.com}; 1847584SAli.Saidi@arm.com 1857584SAli.Saidi@arm.com#endif //__DEV_ARM_PL011_H__ 186