hdlcd.hh revision 11359
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2010-2013, 2015 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Chris Emmons 387405SAli.Saidi@ARM.com * Andreas Sandberg 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com 4210461SAndreas.Sandberg@ARM.com/** @file 439050Schander.sudanthi@arm.com * Implementiation of the ARM HDLcd controller. 448887Sgeoffrey.blake@arm.com * 4510461SAndreas.Sandberg@ARM.com * This implementation aims to have sufficient detail such that underrun 468232Snate@binkert.org * conditions are reasonable / behave similar to reality. There are two 478232Snate@binkert.org * 'engines' going at once. First, the DMA engine running at LCD clock 4810844Sandreas.sandberg@arm.com * frequency is responsible for filling the controller's internal buffer. 499384SAndreas.Sandberg@arm.com * The second engine runs at the pixel clock frequency and reads the pixels 507678Sgblack@eecs.umich.edu * out of the internal buffer. The pixel rendering engine uses front / back 518059SAli.Saidi@ARM.com * porch and sync delays between lines and frames. 528284SAli.Saidi@ARM.com * 537405SAli.Saidi@ARM.com * If the pixel rendering engine does not have a pixel to display, it will 547405SAli.Saidi@ARM.com * cause an underrun event. The HDLcd controller, per spec, will stop 557405SAli.Saidi@ARM.com * issuing DMA requests for the rest of the frame and resume normal behavior 567405SAli.Saidi@ARM.com * on the subsequent frame. What pixels are rendered upon an underrun 5710037SARM gem5 Developers * condition is different than the real hardware; while the user will see 5810037SARM gem5 Developers * artifacts (previous frame mixed with current frame), it is not the same 5911768SCurtis.Dunham@arm.com * behavior as real hardware which repeats the last pixel value for the rest 6010037SARM gem5 Developers * of the current frame. This compromise was made to save on memory and 6110037SARM gem5 Developers * complexity and assumes that it is not important to accurately model the 6210037SARM gem5 Developers * content of an underrun frame. 6310037SARM gem5 Developers * 6411768SCurtis.Dunham@arm.com * KNOWN ISSUES 6510037SARM gem5 Developers * <ul> 6610037SARM gem5 Developers * <li>The HDLcd is implemented here as an AmbaDmaDevice, but it 6711768SCurtis.Dunham@arm.com * doesn't have an AMBA ID as far as I know. That is the only 6811768SCurtis.Dunham@arm.com * bit of the AmbaDmaDevice interface that is irrelevant to it, 6911768SCurtis.Dunham@arm.com * so a fake AMBA ID is used for now. I didn't think inserting 7011768SCurtis.Dunham@arm.com * an extra layer of hierachy between AmbaDmaDevice and 7111768SCurtis.Dunham@arm.com * DmaDevice would be helpful to anyone else, but that may be 7211768SCurtis.Dunham@arm.com * the right answer. 7311768SCurtis.Dunham@arm.com * </ul> 7411768SCurtis.Dunham@arm.com */ 7511768SCurtis.Dunham@arm.com 7611768SCurtis.Dunham@arm.com#ifndef __DEV_ARM_HDLCD_HH__ 7711768SCurtis.Dunham@arm.com#define __DEV_ARM_HDLCD_HH__ 7811768SCurtis.Dunham@arm.com 7910037SARM gem5 Developers#include <fstream> 8010037SARM gem5 Developers#include <memory> 8110037SARM gem5 Developers 8211768SCurtis.Dunham@arm.com#include "base/bitmap.hh" 8311768SCurtis.Dunham@arm.com#include "base/framebuffer.hh" 8411768SCurtis.Dunham@arm.com#include "base/output.hh" 8511768SCurtis.Dunham@arm.com#include "dev/arm/amba_device.hh" 8611768SCurtis.Dunham@arm.com#include "dev/pixelpump.hh" 8711768SCurtis.Dunham@arm.com#include "sim/serialize.hh" 8811768SCurtis.Dunham@arm.com 8911768SCurtis.Dunham@arm.comclass VncInput; 9010037SARM gem5 Developersstruct HDLcdParams; 9111768SCurtis.Dunham@arm.comclass HDLcdPixelPump; 9211768SCurtis.Dunham@arm.com 9311768SCurtis.Dunham@arm.comclass HDLcd: public AmbaDmaDevice 9411768SCurtis.Dunham@arm.com{ 9510037SARM gem5 Developers public: 9611768SCurtis.Dunham@arm.com HDLcd(const HDLcdParams *p); 9711768SCurtis.Dunham@arm.com ~HDLcd(); 9811768SCurtis.Dunham@arm.com 9911768SCurtis.Dunham@arm.com void regStats() override; 10011768SCurtis.Dunham@arm.com 10111768SCurtis.Dunham@arm.com void serialize(CheckpointOut &cp) const override; 10211768SCurtis.Dunham@arm.com void unserialize(CheckpointIn &cp) override; 10311768SCurtis.Dunham@arm.com 10411768SCurtis.Dunham@arm.com void drainResume() override; 10511768SCurtis.Dunham@arm.com 10611768SCurtis.Dunham@arm.com public: // IO device interface 10711768SCurtis.Dunham@arm.com Tick read(PacketPtr pkt) override; 10811768SCurtis.Dunham@arm.com Tick write(PacketPtr pkt) override; 10911768SCurtis.Dunham@arm.com 11011768SCurtis.Dunham@arm.com AddrRangeList getAddrRanges() const override { return addrRanges; } 11111768SCurtis.Dunham@arm.com 11211768SCurtis.Dunham@arm.com protected: // Parameters 11311768SCurtis.Dunham@arm.com VncInput *vnc; 11410037SARM gem5 Developers const bool workaroundSwapRB; 11511768SCurtis.Dunham@arm.com const bool workaroundDmaLineCount; 11611768SCurtis.Dunham@arm.com const AddrRangeList addrRanges; 11711768SCurtis.Dunham@arm.com const bool enableCapture; 11811768SCurtis.Dunham@arm.com const Addr pixelBufferSize; 11910037SARM gem5 Developers 12011768SCurtis.Dunham@arm.com protected: // Register handling 12111768SCurtis.Dunham@arm.com /** ARM HDLcd register offsets */ 12211768SCurtis.Dunham@arm.com enum RegisterOffset { 12311768SCurtis.Dunham@arm.com Version = 0x0000, 12411768SCurtis.Dunham@arm.com Int_RawStat = 0x0010, 12511768SCurtis.Dunham@arm.com Int_Clear = 0x0014, 12610037SARM gem5 Developers Int_Mask = 0x0018, 12711768SCurtis.Dunham@arm.com Int_Status = 0x001C, 12811768SCurtis.Dunham@arm.com Fb_Base = 0x0100, 12911768SCurtis.Dunham@arm.com Fb_Line_Length = 0x0104, 13011768SCurtis.Dunham@arm.com Fb_Line_Count = 0x0108, 13111768SCurtis.Dunham@arm.com Fb_Line_Pitch = 0x010C, 13211768SCurtis.Dunham@arm.com Bus_Options = 0x0110, 13311768SCurtis.Dunham@arm.com V_Sync = 0x0200, 13411768SCurtis.Dunham@arm.com V_Back_Porch = 0x0204, 13511768SCurtis.Dunham@arm.com V_Data = 0x0208, 13611768SCurtis.Dunham@arm.com V_Front_Porch = 0x020C, 13711768SCurtis.Dunham@arm.com H_Sync = 0x0210, 13811768SCurtis.Dunham@arm.com H_Back_Porch = 0x0214, 13911768SCurtis.Dunham@arm.com H_Data = 0x0218, 14011768SCurtis.Dunham@arm.com H_Front_Porch = 0x021C, 14111768SCurtis.Dunham@arm.com Polarities = 0x0220, 14211768SCurtis.Dunham@arm.com Command = 0x0230, 14311768SCurtis.Dunham@arm.com Pixel_Format = 0x0240, 14411768SCurtis.Dunham@arm.com Red_Select = 0x0244, 14511768SCurtis.Dunham@arm.com Green_Select = 0x0248, 14611768SCurtis.Dunham@arm.com Blue_Select = 0x024C, 14711768SCurtis.Dunham@arm.com }; 14811768SCurtis.Dunham@arm.com 14911768SCurtis.Dunham@arm.com /** Reset value for Bus_Options register */ 15011768SCurtis.Dunham@arm.com static constexpr size_t BUS_OPTIONS_RESETV = 0x408; 15111768SCurtis.Dunham@arm.com 15211768SCurtis.Dunham@arm.com /** Reset value for Version register */ 15311768SCurtis.Dunham@arm.com static constexpr size_t VERSION_RESETV = 0x1CDC0000; 15411768SCurtis.Dunham@arm.com 15511768SCurtis.Dunham@arm.com /** AXI port width in bytes */ 15611768SCurtis.Dunham@arm.com static constexpr size_t AXI_PORT_WIDTH = 8; 15711768SCurtis.Dunham@arm.com 15811768SCurtis.Dunham@arm.com /** max number of beats delivered in one dma burst */ 15911768SCurtis.Dunham@arm.com static constexpr size_t MAX_BURST_LEN = 16; 16011768SCurtis.Dunham@arm.com 16111768SCurtis.Dunham@arm.com /** Maximum number of bytes per pixel */ 16211768SCurtis.Dunham@arm.com static constexpr size_t MAX_PIXEL_SIZE = 4; 16311768SCurtis.Dunham@arm.com 16411768SCurtis.Dunham@arm.com /** 16511768SCurtis.Dunham@arm.com * @name RegisterFieldLayouts 16611768SCurtis.Dunham@arm.com * Bit layout declarations for multi-field registers. 16711768SCurtis.Dunham@arm.com */ 16811768SCurtis.Dunham@arm.com /**@{*/ 16911768SCurtis.Dunham@arm.com BitUnion32(VersionReg) 17011768SCurtis.Dunham@arm.com Bitfield<7,0> version_minor; 17111768SCurtis.Dunham@arm.com Bitfield<15,8> version_major; 17211768SCurtis.Dunham@arm.com Bitfield<31,16> product_id; 17311768SCurtis.Dunham@arm.com EndBitUnion(VersionReg) 17411768SCurtis.Dunham@arm.com 17511768SCurtis.Dunham@arm.com static constexpr uint32_t INT_DMA_END = (1UL << 0); 17611768SCurtis.Dunham@arm.com static constexpr uint32_t INT_BUS_ERROR = (1UL << 1); 17711768SCurtis.Dunham@arm.com static constexpr uint32_t INT_VSYNC = (1UL << 2); 17811768SCurtis.Dunham@arm.com static constexpr uint32_t INT_UNDERRUN = (1UL << 3); 17911768SCurtis.Dunham@arm.com 18011768SCurtis.Dunham@arm.com BitUnion32(FbLineCountReg) 18111768SCurtis.Dunham@arm.com Bitfield<11,0> fb_line_count; 18211768SCurtis.Dunham@arm.com Bitfield<31,12> reserved_31_12; 18311768SCurtis.Dunham@arm.com EndBitUnion(FbLineCountReg) 18411768SCurtis.Dunham@arm.com 18511768SCurtis.Dunham@arm.com BitUnion32(BusOptsReg) 18611768SCurtis.Dunham@arm.com Bitfield<4,0> burst_len; 18711768SCurtis.Dunham@arm.com Bitfield<7,5> reserved_7_5; 18811768SCurtis.Dunham@arm.com Bitfield<11,8> max_outstanding; 18911768SCurtis.Dunham@arm.com Bitfield<31,12> reserved_31_12; 19011768SCurtis.Dunham@arm.com EndBitUnion(BusOptsReg) 19111768SCurtis.Dunham@arm.com 19211768SCurtis.Dunham@arm.com BitUnion32(TimingReg) 19311768SCurtis.Dunham@arm.com Bitfield<11,0> val; 19411768SCurtis.Dunham@arm.com Bitfield<31,12> reserved_31_12; 19511768SCurtis.Dunham@arm.com EndBitUnion(TimingReg) 19611768SCurtis.Dunham@arm.com 19711768SCurtis.Dunham@arm.com BitUnion32(PolaritiesReg) 19811768SCurtis.Dunham@arm.com Bitfield<0> vsync_polarity; 19911768SCurtis.Dunham@arm.com Bitfield<1> hsync_polarity; 20011768SCurtis.Dunham@arm.com Bitfield<2> dataen_polarity; 20111768SCurtis.Dunham@arm.com Bitfield<3> data_polarity; 20211768SCurtis.Dunham@arm.com Bitfield<4> pxlclk_polarity; 20311768SCurtis.Dunham@arm.com Bitfield<31,5> reserved_31_5; 20410037SARM gem5 Developers EndBitUnion(PolaritiesReg) 20510037SARM gem5 Developers 20610037SARM gem5 Developers BitUnion32(CommandReg) 2079384SAndreas.Sandberg@arm.com Bitfield<0> enable; 20810461SAndreas.Sandberg@ARM.com Bitfield<31,1> reserved_31_1; 20910461SAndreas.Sandberg@ARM.com EndBitUnion(CommandReg) 21011165SRekai.GonzalezAlberquilla@arm.com 21110461SAndreas.Sandberg@ARM.com BitUnion32(PixelFormatReg) 21210461SAndreas.Sandberg@ARM.com Bitfield<2,0> reserved_2_0; 2139384SAndreas.Sandberg@arm.com Bitfield<4,3> bytes_per_pixel; 21411770SCurtis.Dunham@arm.com Bitfield<30,5> reserved_30_5; 21510037SARM gem5 Developers Bitfield<31> big_endian; 21610461SAndreas.Sandberg@ARM.com EndBitUnion(PixelFormatReg) 21710461SAndreas.Sandberg@ARM.com 21810461SAndreas.Sandberg@ARM.com BitUnion32(ColorSelectReg) 21910461SAndreas.Sandberg@ARM.com Bitfield<4,0> offset; 22010461SAndreas.Sandberg@ARM.com Bitfield<7,5> reserved_7_5; 22110461SAndreas.Sandberg@ARM.com Bitfield<11,8> size; 22210609Sandreas.sandberg@arm.com Bitfield<15,12> reserved_15_12; 22310609Sandreas.sandberg@arm.com Bitfield<23,16> default_color; 22410609Sandreas.sandberg@arm.com Bitfield<31,24> reserved_31_24; 22510037SARM gem5 Developers EndBitUnion(ColorSelectReg) 22610037SARM gem5 Developers /**@}*/ 22710037SARM gem5 Developers 22810037SARM gem5 Developers /** 22910037SARM gem5 Developers * @name HDLCDRegisters 23010037SARM gem5 Developers * HDLCD register contents. 23110037SARM gem5 Developers */ 23210037SARM gem5 Developers /**@{*/ 23310037SARM gem5 Developers const VersionReg version; /**< Version register */ 23410037SARM gem5 Developers uint32_t int_rawstat; /**< Interrupt raw status register */ 23510037SARM gem5 Developers uint32_t int_mask; /**< Interrupt mask register */ 23610037SARM gem5 Developers uint32_t fb_base; /**< Frame buffer base address register */ 23710037SARM gem5 Developers uint32_t fb_line_length; /**< Frame buffer Line length register */ 23810037SARM gem5 Developers FbLineCountReg fb_line_count; /**< Frame buffer Line count register */ 23910037SARM gem5 Developers int32_t fb_line_pitch; /**< Frame buffer Line pitch register */ 24010037SARM gem5 Developers BusOptsReg bus_options; /**< Bus options register */ 24111768SCurtis.Dunham@arm.com TimingReg v_sync; /**< Vertical sync width register */ 24211768SCurtis.Dunham@arm.com TimingReg v_back_porch; /**< Vertical back porch width register */ 24310037SARM gem5 Developers TimingReg v_data; /**< Vertical data width register */ 24410037SARM gem5 Developers TimingReg v_front_porch; /**< Vertical front porch width register */ 24510037SARM gem5 Developers TimingReg h_sync; /**< Horizontal sync width register */ 24610037SARM gem5 Developers TimingReg h_back_porch; /**< Horizontal back porch width register */ 2479384SAndreas.Sandberg@arm.com TimingReg h_data; /**< Horizontal data width register */ 2489384SAndreas.Sandberg@arm.com TimingReg h_front_porch; /**< Horizontal front porch width reg */ 2499384SAndreas.Sandberg@arm.com PolaritiesReg polarities; /**< Polarities register */ 2509384SAndreas.Sandberg@arm.com CommandReg command; /**< Command register */ 2519384SAndreas.Sandberg@arm.com PixelFormatReg pixel_format; /**< Pixel format register */ 2529384SAndreas.Sandberg@arm.com ColorSelectReg red_select; /**< Red color select register */ 2539384SAndreas.Sandberg@arm.com ColorSelectReg green_select; /**< Green color select register */ 2549384SAndreas.Sandberg@arm.com ColorSelectReg blue_select; /**< Blue color select register */ 2559384SAndreas.Sandberg@arm.com /** @} */ 2567427Sgblack@eecs.umich.edu 2577427Sgblack@eecs.umich.edu uint32_t readReg(Addr offset); 2587427Sgblack@eecs.umich.edu void writeReg(Addr offset, uint32_t value); 2599385SAndreas.Sandberg@arm.com 2609385SAndreas.Sandberg@arm.com PixelConverter pixelConverter() const; 2617427Sgblack@eecs.umich.edu DisplayTimings displayTimings() const; 2627427Sgblack@eecs.umich.edu 26310037SARM gem5 Developers void createDmaEngine(); 26410037SARM gem5 Developers 26510037SARM gem5 Developers void cmdEnable(); 26610037SARM gem5 Developers void cmdDisable(); 26710037SARM gem5 Developers 26810037SARM gem5 Developers bool enabled() const { return command.enable; } 26910037SARM gem5 Developers 27010037SARM gem5 Developers public: // Pixel pump callbacks 27110037SARM gem5 Developers bool pxlNext(Pixel &p); 27210037SARM gem5 Developers void pxlVSyncBegin(); 27310037SARM gem5 Developers void pxlVSyncEnd(); 27410037SARM gem5 Developers void pxlUnderrun(); 27510037SARM gem5 Developers void pxlFrameDone(); 27610037SARM gem5 Developers 2777427Sgblack@eecs.umich.edu protected: // Interrupt handling 2787427Sgblack@eecs.umich.edu /** 2797427Sgblack@eecs.umich.edu * Assign new interrupt values and update interrupt signals 2807427Sgblack@eecs.umich.edu * 2817427Sgblack@eecs.umich.edu * A new interrupt is scheduled signalled if the set of unmasked 2827427Sgblack@eecs.umich.edu * interrupts goes empty to non-empty. Conversely, if the set of 28310037SARM gem5 Developers * unmasked interrupts goes from non-empty to empty, the interrupt 28410037SARM gem5 Developers * signal is cleared. 28510037SARM gem5 Developers * 28610037SARM gem5 Developers * @param ints New <i>raw</i> interrupt status 2877427Sgblack@eecs.umich.edu * @param mask New interrupt mask 2887427Sgblack@eecs.umich.edu */ 2897427Sgblack@eecs.umich.edu void setInterrupts(uint32_t ints, uint32_t mask); 29010037SARM gem5 Developers 29110204SAli.Saidi@ARM.com /** 29210204SAli.Saidi@ARM.com * Convenience function to update the interrupt mask 29310037SARM gem5 Developers * 2947427Sgblack@eecs.umich.edu * @see setInterrupts 29510037SARM gem5 Developers * @param mask New interrupt mask 2967427Sgblack@eecs.umich.edu */ 29710037SARM gem5 Developers void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); } 2987427Sgblack@eecs.umich.edu 2997427Sgblack@eecs.umich.edu /** 30010037SARM gem5 Developers * Convenience function to raise a new interrupt 3017427Sgblack@eecs.umich.edu * 3027427Sgblack@eecs.umich.edu * @see setInterrupts 3037427Sgblack@eecs.umich.edu * @param ints Set of interrupts to raise 3047427Sgblack@eecs.umich.edu */ 3057427Sgblack@eecs.umich.edu void intRaise(uint32_t ints) { 3067427Sgblack@eecs.umich.edu setInterrupts(int_rawstat | ints, int_mask); 3077427Sgblack@eecs.umich.edu } 3087427Sgblack@eecs.umich.edu 3097427Sgblack@eecs.umich.edu /** 3107427Sgblack@eecs.umich.edu * Convenience function to clear interrupts 3117427Sgblack@eecs.umich.edu * 3127427Sgblack@eecs.umich.edu * @see setInterrupts 3137427Sgblack@eecs.umich.edu * @param ints Set of interrupts to clear 3147427Sgblack@eecs.umich.edu */ 3157427Sgblack@eecs.umich.edu void intClear(uint32_t ints) { 3167427Sgblack@eecs.umich.edu setInterrupts(int_rawstat & ~ints, int_mask); 3177427Sgblack@eecs.umich.edu } 3187427Sgblack@eecs.umich.edu 3197427Sgblack@eecs.umich.edu /** Masked interrupt status register */ 3207427Sgblack@eecs.umich.edu uint32_t intStatus() const { return int_rawstat & int_mask; } 3217427Sgblack@eecs.umich.edu 3227427Sgblack@eecs.umich.edu protected: // Pixel output 3237427Sgblack@eecs.umich.edu class PixelPump : public BasePixelPump 3247436Sdam.sunwoo@arm.com { 3257436Sdam.sunwoo@arm.com public: 32610037SARM gem5 Developers PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk) 32710037SARM gem5 Developers : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p) {} 3287436Sdam.sunwoo@arm.com 3297436Sdam.sunwoo@arm.com void dumpSettings(); 3307436Sdam.sunwoo@arm.com 3317436Sdam.sunwoo@arm.com protected: 3327436Sdam.sunwoo@arm.com bool nextPixel(Pixel &p) override { return parent.pxlNext(p); } 3337436Sdam.sunwoo@arm.com 3347436Sdam.sunwoo@arm.com void onVSyncBegin() override { return parent.pxlVSyncBegin(); } 3357436Sdam.sunwoo@arm.com void onVSyncEnd() override { return parent.pxlVSyncEnd(); } 3367436Sdam.sunwoo@arm.com 3377436Sdam.sunwoo@arm.com void onUnderrun(unsigned x, unsigned y) override { 3387436Sdam.sunwoo@arm.com parent.pxlUnderrun(); 3397436Sdam.sunwoo@arm.com } 34010037SARM gem5 Developers 3417436Sdam.sunwoo@arm.com void onFrameDone() override { parent.pxlFrameDone(); } 3427436Sdam.sunwoo@arm.com 3437436Sdam.sunwoo@arm.com protected: 3447436Sdam.sunwoo@arm.com HDLcd &parent; 3457436Sdam.sunwoo@arm.com }; 3467436Sdam.sunwoo@arm.com 3477436Sdam.sunwoo@arm.com /** Helper to write out bitmaps */ 3487436Sdam.sunwoo@arm.com Bitmap bmp; 3497436Sdam.sunwoo@arm.com 3507436Sdam.sunwoo@arm.com /** Picture of what the current frame buffer looks like */ 3517436Sdam.sunwoo@arm.com OutputStream *pic; 3527436Sdam.sunwoo@arm.com 3537436Sdam.sunwoo@arm.com /** Cached pixel converter, set when the converter is enabled. */ 3547436Sdam.sunwoo@arm.com PixelConverter conv; 3557436Sdam.sunwoo@arm.com 3567436Sdam.sunwoo@arm.com PixelPump pixelPump; 3577644Sali.saidi@arm.com 3588147SAli.Saidi@ARM.com protected: // DMA handling 3599385SAndreas.Sandberg@arm.com class DmaEngine : public DmaReadFifo 3609385SAndreas.Sandberg@arm.com { 3619385SAndreas.Sandberg@arm.com public: 3629385SAndreas.Sandberg@arm.com DmaEngine(HDLcd &_parent, size_t size, 3639385SAndreas.Sandberg@arm.com unsigned request_size, unsigned max_pending, 3649385SAndreas.Sandberg@arm.com size_t line_size, ssize_t line_pitch, unsigned num_lines); 3659385SAndreas.Sandberg@arm.com 3669385SAndreas.Sandberg@arm.com void startFrame(Addr fb_base); 3679385SAndreas.Sandberg@arm.com void abortFrame(); 3689385SAndreas.Sandberg@arm.com void dumpSettings(); 3699385SAndreas.Sandberg@arm.com 3709385SAndreas.Sandberg@arm.com void serialize(CheckpointOut &cp) const override; 3719385SAndreas.Sandberg@arm.com void unserialize(CheckpointIn &cp) override; 3729385SAndreas.Sandberg@arm.com 3739385SAndreas.Sandberg@arm.com protected: 3749385SAndreas.Sandberg@arm.com void onEndOfBlock() override; 3759385SAndreas.Sandberg@arm.com void onIdle() override; 3769385SAndreas.Sandberg@arm.com 37710037SARM gem5 Developers HDLcd &parent; 37810037SARM gem5 Developers const size_t lineSize; 37910037SARM gem5 Developers const ssize_t linePitch; 38010037SARM gem5 Developers const unsigned numLines; 38110037SARM gem5 Developers 38210037SARM gem5 Developers Addr nextLineAddr; 38310037SARM gem5 Developers Addr frameEnd; 38410037SARM gem5 Developers }; 38510037SARM gem5 Developers 38610037SARM gem5 Developers std::unique_ptr<DmaEngine> dmaEngine; 38710037SARM gem5 Developers 38810037SARM gem5 Developers protected: // Statistics 38910037SARM gem5 Developers struct { 39010037SARM gem5 Developers Stats::Scalar underruns; 39110037SARM gem5 Developers } stats; 39210037SARM gem5 Developers}; 3938147SAli.Saidi@ARM.com 3947427Sgblack@eecs.umich.edu#endif 3957427Sgblack@eecs.umich.edu