hdlcd.hh revision 11168
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2010-2013, 2015 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Chris Emmons 387405SAli.Saidi@ARM.com * Andreas Sandberg 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com 4210461SAndreas.Sandberg@ARM.com/** @file 439050Schander.sudanthi@arm.com * Implementiation of the ARM HDLcd controller. 4412406Sgabeblack@google.com * 4511793Sbrandon.potter@amd.com * This implementation aims to have sufficient detail such that underrun 468887Sgeoffrey.blake@arm.com * conditions are reasonable / behave similar to reality. There are two 478232Snate@binkert.org * 'engines' going at once. First, the DMA engine running at LCD clock 488232Snate@binkert.org * frequency is responsible for filling the controller's internal buffer. 4910844Sandreas.sandberg@arm.com * The second engine runs at the pixel clock frequency and reads the pixels 509384SAndreas.Sandberg@arm.com * out of the internal buffer. The pixel rendering engine uses front / back 517678Sgblack@eecs.umich.edu * porch and sync delays between lines and frames. 528059SAli.Saidi@ARM.com * 538284SAli.Saidi@ARM.com * If the pixel rendering engine does not have a pixel to display, it will 547405SAli.Saidi@ARM.com * cause an underrun event. The HDLcd controller, per spec, will stop 557405SAli.Saidi@ARM.com * issuing DMA requests for the rest of the frame and resume normal behavior 567405SAli.Saidi@ARM.com * on the subsequent frame. What pixels are rendered upon an underrun 577405SAli.Saidi@ARM.com * condition is different than the real hardware; while the user will see 589384SAndreas.Sandberg@arm.com * artifacts (previous frame mixed with current frame), it is not the same 5910461SAndreas.Sandberg@ARM.com * behavior as real hardware which repeats the last pixel value for the rest 6010461SAndreas.Sandberg@ARM.com * of the current frame. This compromise was made to save on memory and 6111165SRekai.GonzalezAlberquilla@arm.com * complexity and assumes that it is not important to accurately model the 6212109SRekai.GonzalezAlberquilla@arm.com * content of an underrun frame. 6312479SCurtis.Dunham@arm.com * 649384SAndreas.Sandberg@arm.com * KNOWN ISSUES 6511770SCurtis.Dunham@arm.com * <ul> 6610037SARM gem5 Developers * <li>The HDLcd is implemented here as an AmbaDmaDevice, but it 6710461SAndreas.Sandberg@ARM.com * doesn't have an AMBA ID as far as I know. That is the only 6810461SAndreas.Sandberg@ARM.com * bit of the AmbaDmaDevice interface that is irrelevant to it, 6910461SAndreas.Sandberg@ARM.com * so a fake AMBA ID is used for now. I didn't think inserting 7010461SAndreas.Sandberg@ARM.com * an extra layer of hierachy between AmbaDmaDevice and 7110461SAndreas.Sandberg@ARM.com * DmaDevice would be helpful to anyone else, but that may be 7210461SAndreas.Sandberg@ARM.com * the right answer. 7310609Sandreas.sandberg@arm.com * </ul> 7410609Sandreas.sandberg@arm.com */ 7510609Sandreas.sandberg@arm.com 7610037SARM gem5 Developers#ifndef __DEV_ARM_HDLCD_HH__ 7710037SARM gem5 Developers#define __DEV_ARM_HDLCD_HH__ 7810037SARM gem5 Developers 7910037SARM gem5 Developers#include <fstream> 8011771SCurtis.Dunham@arm.com#include <memory> 8110037SARM gem5 Developers 8210037SARM gem5 Developers#include "base/bitmap.hh" 8310037SARM gem5 Developers#include "base/framebuffer.hh" 8410037SARM gem5 Developers#include "dev/arm/amba_device.hh" 8510037SARM gem5 Developers#include "dev/pixelpump.hh" 8610037SARM gem5 Developers#include "sim/serialize.hh" 8711771SCurtis.Dunham@arm.com 8810037SARM gem5 Developersclass VncInput; 8910037SARM gem5 Developersstruct HDLcdParams; 9010037SARM gem5 Developersclass HDLcdPixelPump; 9110037SARM gem5 Developers 9210037SARM gem5 Developersclass HDLcd: public AmbaDmaDevice 9312477SCurtis.Dunham@arm.com{ 9410037SARM gem5 Developers public: 9510037SARM gem5 Developers HDLcd(const HDLcdParams *p); 969384SAndreas.Sandberg@arm.com ~HDLcd(); 979384SAndreas.Sandberg@arm.com 989384SAndreas.Sandberg@arm.com void regStats() override; 9912479SCurtis.Dunham@arm.com 10012479SCurtis.Dunham@arm.com void serialize(CheckpointOut &cp) const override; 1019384SAndreas.Sandberg@arm.com void unserialize(CheckpointIn &cp) override; 1029384SAndreas.Sandberg@arm.com 1039384SAndreas.Sandberg@arm.com void drainResume() override; 1049384SAndreas.Sandberg@arm.com 1059384SAndreas.Sandberg@arm.com public: // IO device interface 1069384SAndreas.Sandberg@arm.com Tick read(PacketPtr pkt) override; 1077427Sgblack@eecs.umich.edu Tick write(PacketPtr pkt) override; 1087427Sgblack@eecs.umich.edu 1097427Sgblack@eecs.umich.edu AddrRangeList getAddrRanges() const override { return addrRanges; } 1109385SAndreas.Sandberg@arm.com 1119385SAndreas.Sandberg@arm.com protected: // Parameters 1127427Sgblack@eecs.umich.edu VncInput *vnc; 1137427Sgblack@eecs.umich.edu const bool workaroundSwapRB; 11410037SARM gem5 Developers const bool workaroundDmaLineCount; 11510037SARM gem5 Developers const AddrRangeList addrRanges; 11610037SARM gem5 Developers const bool enableCapture; 11710037SARM gem5 Developers const Addr pixelBufferSize; 11810037SARM gem5 Developers 11910037SARM gem5 Developers protected: // Register handling 12010037SARM gem5 Developers /** ARM HDLcd register offsets */ 12110037SARM gem5 Developers enum RegisterOffset { 12210037SARM gem5 Developers Version = 0x0000, 12310037SARM gem5 Developers Int_RawStat = 0x0010, 12410037SARM gem5 Developers Int_Clear = 0x0014, 12510037SARM gem5 Developers Int_Mask = 0x0018, 12610037SARM gem5 Developers Int_Status = 0x001C, 12710037SARM gem5 Developers Fb_Base = 0x0100, 1287427Sgblack@eecs.umich.edu Fb_Line_Length = 0x0104, 1297427Sgblack@eecs.umich.edu Fb_Line_Count = 0x0108, 1307427Sgblack@eecs.umich.edu Fb_Line_Pitch = 0x010C, 1317427Sgblack@eecs.umich.edu Bus_Options = 0x0110, 1327427Sgblack@eecs.umich.edu V_Sync = 0x0200, 1337427Sgblack@eecs.umich.edu V_Back_Porch = 0x0204, 13410037SARM gem5 Developers V_Data = 0x0208, 13510037SARM gem5 Developers V_Front_Porch = 0x020C, 13610037SARM gem5 Developers H_Sync = 0x0210, 13710037SARM gem5 Developers H_Back_Porch = 0x0214, 1387427Sgblack@eecs.umich.edu H_Data = 0x0218, 1397427Sgblack@eecs.umich.edu H_Front_Porch = 0x021C, 1407427Sgblack@eecs.umich.edu Polarities = 0x0220, 14110037SARM gem5 Developers Command = 0x0230, 14210204SAli.Saidi@ARM.com Pixel_Format = 0x0240, 14310204SAli.Saidi@ARM.com Red_Select = 0x0244, 14410037SARM gem5 Developers Green_Select = 0x0248, 1457427Sgblack@eecs.umich.edu Blue_Select = 0x024C, 14610037SARM gem5 Developers }; 1477427Sgblack@eecs.umich.edu 14810037SARM gem5 Developers /** Reset value for Bus_Options register */ 1497427Sgblack@eecs.umich.edu static constexpr size_t BUS_OPTIONS_RESETV = 0x408; 1507427Sgblack@eecs.umich.edu 15110037SARM gem5 Developers /** Reset value for Version register */ 1527427Sgblack@eecs.umich.edu static constexpr size_t VERSION_RESETV = 0x1CDC0000; 1537427Sgblack@eecs.umich.edu 1547427Sgblack@eecs.umich.edu /** AXI port width in bytes */ 1557427Sgblack@eecs.umich.edu static constexpr size_t AXI_PORT_WIDTH = 8; 1567427Sgblack@eecs.umich.edu 1577427Sgblack@eecs.umich.edu /** max number of beats delivered in one dma burst */ 1587427Sgblack@eecs.umich.edu static constexpr size_t MAX_BURST_LEN = 16; 1597427Sgblack@eecs.umich.edu 1607427Sgblack@eecs.umich.edu /** Maximum number of bytes per pixel */ 1617427Sgblack@eecs.umich.edu static constexpr size_t MAX_PIXEL_SIZE = 4; 1627427Sgblack@eecs.umich.edu 1637427Sgblack@eecs.umich.edu /** 1647427Sgblack@eecs.umich.edu * @name RegisterFieldLayouts 1657427Sgblack@eecs.umich.edu * Bit layout declarations for multi-field registers. 1667427Sgblack@eecs.umich.edu */ 1677427Sgblack@eecs.umich.edu /**@{*/ 1687427Sgblack@eecs.umich.edu BitUnion32(VersionReg) 1697427Sgblack@eecs.umich.edu Bitfield<7,0> version_minor; 1707427Sgblack@eecs.umich.edu Bitfield<15,8> version_major; 1717427Sgblack@eecs.umich.edu Bitfield<31,16> product_id; 1727427Sgblack@eecs.umich.edu EndBitUnion(VersionReg) 1737427Sgblack@eecs.umich.edu 1747427Sgblack@eecs.umich.edu static constexpr uint32_t INT_DMA_END = (1UL << 0); 1757436Sdam.sunwoo@arm.com static constexpr uint32_t INT_BUS_ERROR = (1UL << 1); 1767436Sdam.sunwoo@arm.com static constexpr uint32_t INT_VSYNC = (1UL << 2); 17710037SARM gem5 Developers static constexpr uint32_t INT_UNDERRUN = (1UL << 3); 17810037SARM gem5 Developers 1797436Sdam.sunwoo@arm.com BitUnion32(FbLineCountReg) 1807436Sdam.sunwoo@arm.com Bitfield<11,0> fb_line_count; 1817436Sdam.sunwoo@arm.com Bitfield<31,12> reserved_31_12; 1827436Sdam.sunwoo@arm.com EndBitUnion(FbLineCountReg) 1837436Sdam.sunwoo@arm.com 1847436Sdam.sunwoo@arm.com BitUnion32(BusOptsReg) 1857436Sdam.sunwoo@arm.com Bitfield<4,0> burst_len; 1867436Sdam.sunwoo@arm.com Bitfield<7,5> reserved_7_5; 1877436Sdam.sunwoo@arm.com Bitfield<11,8> max_outstanding; 1887436Sdam.sunwoo@arm.com Bitfield<31,12> reserved_31_12; 1897436Sdam.sunwoo@arm.com EndBitUnion(BusOptsReg) 1907436Sdam.sunwoo@arm.com 19110037SARM gem5 Developers BitUnion32(TimingReg) 1927436Sdam.sunwoo@arm.com Bitfield<11,0> val; 1937436Sdam.sunwoo@arm.com Bitfield<31,12> reserved_31_12; 1947436Sdam.sunwoo@arm.com EndBitUnion(TimingReg) 1957436Sdam.sunwoo@arm.com 1967436Sdam.sunwoo@arm.com BitUnion32(PolaritiesReg) 1977436Sdam.sunwoo@arm.com Bitfield<0> vsync_polarity; 1987436Sdam.sunwoo@arm.com Bitfield<1> hsync_polarity; 1997436Sdam.sunwoo@arm.com Bitfield<2> dataen_polarity; 2007436Sdam.sunwoo@arm.com Bitfield<3> data_polarity; 2017436Sdam.sunwoo@arm.com Bitfield<4> pxlclk_polarity; 2027436Sdam.sunwoo@arm.com Bitfield<31,5> reserved_31_5; 2037436Sdam.sunwoo@arm.com EndBitUnion(PolaritiesReg) 2047436Sdam.sunwoo@arm.com 2057436Sdam.sunwoo@arm.com BitUnion32(CommandReg) 2067436Sdam.sunwoo@arm.com Bitfield<0> enable; 2077436Sdam.sunwoo@arm.com Bitfield<31,1> reserved_31_1; 2087644Sali.saidi@arm.com EndBitUnion(CommandReg) 2098147SAli.Saidi@ARM.com 2109385SAndreas.Sandberg@arm.com BitUnion32(PixelFormatReg) 2119385SAndreas.Sandberg@arm.com Bitfield<2,0> reserved_2_0; 2129385SAndreas.Sandberg@arm.com Bitfield<4,3> bytes_per_pixel; 2139385SAndreas.Sandberg@arm.com Bitfield<30,5> reserved_30_5; 2149385SAndreas.Sandberg@arm.com Bitfield<31> big_endian; 2159385SAndreas.Sandberg@arm.com EndBitUnion(PixelFormatReg) 2169385SAndreas.Sandberg@arm.com 2179385SAndreas.Sandberg@arm.com BitUnion32(ColorSelectReg) 2189385SAndreas.Sandberg@arm.com Bitfield<4,0> offset; 2199385SAndreas.Sandberg@arm.com Bitfield<7,5> reserved_7_5; 2209385SAndreas.Sandberg@arm.com Bitfield<11,8> size; 2219385SAndreas.Sandberg@arm.com Bitfield<15,12> reserved_15_12; 2229385SAndreas.Sandberg@arm.com Bitfield<23,16> default_color; 2239385SAndreas.Sandberg@arm.com Bitfield<31,24> reserved_31_24; 22410037SARM gem5 Developers EndBitUnion(ColorSelectReg) 22510037SARM gem5 Developers /**@}*/ 22610037SARM gem5 Developers 22710037SARM gem5 Developers /** 22810037SARM gem5 Developers * @name HDLCDRegisters 22910037SARM gem5 Developers * HDLCD register contents. 23010037SARM gem5 Developers */ 23110037SARM gem5 Developers /**@{*/ 23210037SARM gem5 Developers const VersionReg version; /**< Version register */ 23310037SARM gem5 Developers uint32_t int_rawstat; /**< Interrupt raw status register */ 23410037SARM gem5 Developers uint32_t int_mask; /**< Interrupt mask register */ 23510037SARM gem5 Developers uint32_t fb_base; /**< Frame buffer base address register */ 23610037SARM gem5 Developers uint32_t fb_line_length; /**< Frame buffer Line length register */ 23710037SARM gem5 Developers FbLineCountReg fb_line_count; /**< Frame buffer Line count register */ 23810037SARM gem5 Developers int32_t fb_line_pitch; /**< Frame buffer Line pitch register */ 23910037SARM gem5 Developers BusOptsReg bus_options; /**< Bus options register */ 2408147SAli.Saidi@ARM.com TimingReg v_sync; /**< Vertical sync width register */ 2417427Sgblack@eecs.umich.edu TimingReg v_back_porch; /**< Vertical back porch width register */ 2427427Sgblack@eecs.umich.edu TimingReg v_data; /**< Vertical data width register */ 2437427Sgblack@eecs.umich.edu TimingReg v_front_porch; /**< Vertical front porch width register */ 24410037SARM gem5 Developers TimingReg h_sync; /**< Horizontal sync width register */ 24510037SARM gem5 Developers TimingReg h_back_porch; /**< Horizontal back porch width register */ 24610037SARM gem5 Developers TimingReg h_data; /**< Horizontal data width register */ 24710037SARM gem5 Developers TimingReg h_front_porch; /**< Horizontal front porch width reg */ 24810037SARM gem5 Developers PolaritiesReg polarities; /**< Polarities register */ 24910037SARM gem5 Developers CommandReg command; /**< Command register */ 25010037SARM gem5 Developers PixelFormatReg pixel_format; /**< Pixel format register */ 25110037SARM gem5 Developers ColorSelectReg red_select; /**< Red color select register */ 25210037SARM gem5 Developers ColorSelectReg green_select; /**< Green color select register */ 25310037SARM gem5 Developers ColorSelectReg blue_select; /**< Blue color select register */ 25410037SARM gem5 Developers /** @} */ 25510037SARM gem5 Developers 25610037SARM gem5 Developers uint32_t readReg(Addr offset); 25710037SARM gem5 Developers void writeReg(Addr offset, uint32_t value); 25810037SARM gem5 Developers 25910037SARM gem5 Developers PixelConverter pixelConverter() const; 26010037SARM gem5 Developers DisplayTimings displayTimings() const; 26110037SARM gem5 Developers 26210037SARM gem5 Developers void createDmaEngine(); 26310037SARM gem5 Developers 26410037SARM gem5 Developers void cmdEnable(); 26510037SARM gem5 Developers void cmdDisable(); 26610037SARM gem5 Developers 26710037SARM gem5 Developers bool enabled() const { return command.enable; } 26810037SARM gem5 Developers 26910037SARM gem5 Developers public: // Pixel pump callbacks 27010037SARM gem5 Developers bool pxlNext(Pixel &p); 27110037SARM gem5 Developers void pxlVSyncBegin(); 27210037SARM gem5 Developers void pxlVSyncEnd(); 27310037SARM gem5 Developers void pxlUnderrun(); 27410037SARM gem5 Developers void pxlFrameDone(); 27510037SARM gem5 Developers 27610037SARM gem5 Developers protected: // Interrupt handling 27710037SARM gem5 Developers /** 27810037SARM gem5 Developers * Assign new interrupt values and update interrupt signals 27910037SARM gem5 Developers * 28011770SCurtis.Dunham@arm.com * A new interrupt is scheduled signalled if the set of unmasked 28110037SARM gem5 Developers * interrupts goes empty to non-empty. Conversely, if the set of 28211574SCurtis.Dunham@arm.com * unmasked interrupts goes from non-empty to empty, the interrupt 28311770SCurtis.Dunham@arm.com * signal is cleared. 28411770SCurtis.Dunham@arm.com * 28510037SARM gem5 Developers * @param ints New <i>raw</i> interrupt status 28611770SCurtis.Dunham@arm.com * @param mask New interrupt mask 28711770SCurtis.Dunham@arm.com */ 28810037SARM gem5 Developers void setInterrupts(uint32_t ints, uint32_t mask); 28910037SARM gem5 Developers 29010037SARM gem5 Developers /** 29110037SARM gem5 Developers * Convenience function to update the interrupt mask 29210037SARM gem5 Developers * 29310037SARM gem5 Developers * @see setInterrupts 29410037SARM gem5 Developers * @param mask New interrupt mask 29510461SAndreas.Sandberg@ARM.com */ 29610461SAndreas.Sandberg@ARM.com void intMask(uint32_t mask) { setInterrupts(int_rawstat, mask); } 29710461SAndreas.Sandberg@ARM.com 29810461SAndreas.Sandberg@ARM.com /** 29910037SARM gem5 Developers * Convenience function to raise a new interrupt 30010037SARM gem5 Developers * 30110037SARM gem5 Developers * @see setInterrupts 30210037SARM gem5 Developers * @param ints Set of interrupts to raise 30310037SARM gem5 Developers */ 30410037SARM gem5 Developers void intRaise(uint32_t ints) { 30510461SAndreas.Sandberg@ARM.com setInterrupts(int_rawstat | ints, int_mask); 30610461SAndreas.Sandberg@ARM.com } 30710461SAndreas.Sandberg@ARM.com 30810461SAndreas.Sandberg@ARM.com /** 30910461SAndreas.Sandberg@ARM.com * Convenience function to clear interrupts 31010037SARM gem5 Developers * 31110037SARM gem5 Developers * @see setInterrupts 31210037SARM gem5 Developers * @param ints Set of interrupts to clear 31310037SARM gem5 Developers */ 31410037SARM gem5 Developers void intClear(uint32_t ints) { 31511574SCurtis.Dunham@arm.com setInterrupts(int_rawstat & ~ints, int_mask); 31610037SARM gem5 Developers } 31710037SARM gem5 Developers 31810037SARM gem5 Developers /** Masked interrupt status register */ 31911574SCurtis.Dunham@arm.com const uint32_t intStatus() const { return int_rawstat & int_mask; } 32010037SARM gem5 Developers 32110037SARM gem5 Developers protected: // Pixel output 32210037SARM gem5 Developers class PixelPump : public BasePixelPump 32310037SARM gem5 Developers { 32410037SARM gem5 Developers public: 32510037SARM gem5 Developers PixelPump(HDLcd &p, ClockDomain &pxl_clk, unsigned pixel_chunk) 32610037SARM gem5 Developers : BasePixelPump(p, pxl_clk, pixel_chunk), parent(p) {} 32710037SARM gem5 Developers 32810037SARM gem5 Developers void dumpSettings(); 32910037SARM gem5 Developers 3307405SAli.Saidi@ARM.com protected: 33110035Sandreas.hansson@arm.com bool nextPixel(Pixel &p) override { return parent.pxlNext(p); } 3327405SAli.Saidi@ARM.com 3337405SAli.Saidi@ARM.com void onVSyncBegin() override { return parent.pxlVSyncBegin(); } 3347614Sminkyu.jeong@arm.com void onVSyncEnd() override { return parent.pxlVSyncEnd(); } 33512478SCurtis.Dunham@arm.com 33612478SCurtis.Dunham@arm.com void onUnderrun(unsigned x, unsigned y) override { 33712478SCurtis.Dunham@arm.com parent.pxlUnderrun(); 33812478SCurtis.Dunham@arm.com } 33912478SCurtis.Dunham@arm.com 34012478SCurtis.Dunham@arm.com void onFrameDone() override { parent.pxlFrameDone(); } 34112478SCurtis.Dunham@arm.com 34212478SCurtis.Dunham@arm.com protected: 34312478SCurtis.Dunham@arm.com HDLcd &parent; 34412478SCurtis.Dunham@arm.com }; 34512478SCurtis.Dunham@arm.com 34612478SCurtis.Dunham@arm.com /** Helper to write out bitmaps */ 34712478SCurtis.Dunham@arm.com Bitmap bmp; 34812478SCurtis.Dunham@arm.com 34912478SCurtis.Dunham@arm.com /** Picture of what the current frame buffer looks like */ 35012478SCurtis.Dunham@arm.com std::ostream *pic; 3517405SAli.Saidi@ARM.com 3527405SAli.Saidi@ARM.com /** Cached pixel converter, set when the converter is enabled. */ 3537405SAli.Saidi@ARM.com PixelConverter conv; 3547405SAli.Saidi@ARM.com 3557405SAli.Saidi@ARM.com PixelPump pixelPump; 3567405SAli.Saidi@ARM.com 35710037SARM gem5 Developers protected: // DMA handling 35810037SARM gem5 Developers class DmaEngine : public DmaReadFifo 35910037SARM gem5 Developers { 3609050Schander.sudanthi@arm.com public: 3617405SAli.Saidi@ARM.com DmaEngine(HDLcd &_parent, size_t size, 36210037SARM gem5 Developers unsigned request_size, unsigned max_pending, 36310037SARM gem5 Developers size_t line_size, ssize_t line_pitch, unsigned num_lines); 3647720Sgblack@eecs.umich.edu 3657720Sgblack@eecs.umich.edu void startFrame(Addr fb_base); 3667405SAli.Saidi@ARM.com void abortFrame(); 3677405SAli.Saidi@ARM.com void dumpSettings(); 3687757SAli.Saidi@ARM.com 36910037SARM gem5 Developers void serialize(CheckpointOut &cp) const override; 37010037SARM gem5 Developers void unserialize(CheckpointIn &cp) override; 37110037SARM gem5 Developers 37210037SARM gem5 Developers protected: 37310037SARM gem5 Developers void onEndOfBlock() override; 37410037SARM gem5 Developers void onIdle() override; 37510037SARM gem5 Developers 37610037SARM gem5 Developers HDLcd &parent; 37710037SARM gem5 Developers const size_t lineSize; 37810037SARM gem5 Developers const ssize_t linePitch; 37910037SARM gem5 Developers const unsigned numLines; 38010037SARM gem5 Developers 38110037SARM gem5 Developers Addr nextLineAddr; 38210037SARM gem5 Developers Addr frameEnd; 38310037SARM gem5 Developers }; 38410037SARM gem5 Developers 38510037SARM gem5 Developers std::unique_ptr<DmaEngine> dmaEngine; 38610037SARM gem5 Developers 38710037SARM gem5 Developers protected: // Statistics 38810037SARM gem5 Developers struct { 38910037SARM gem5 Developers Stats::Scalar underruns; 39010037SARM gem5 Developers } stats; 39110037SARM gem5 Developers}; 39210037SARM gem5 Developers 39310037SARM gem5 Developers#endif 39410037SARM gem5 Developers