gic_v3.hh revision 13996:8a567118e670 
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_H__
32#define __DEV_ARM_GICV3_H__
33
34#include "dev/arm/base_gic.hh"
35#include "params/Gicv3.hh"
36
37class Gicv3CPUInterface;
38class Gicv3Distributor;
39class Gicv3Redistributor;
40class Gicv3Its;
41
42class Gicv3 : public BaseGic
43{
44  protected:
45    friend class Gicv3CPUInterface;
46    friend class Gicv3Redistributor;
47
48    typedef Gicv3Params Params;
49    Gicv3Distributor * distributor;
50    std::vector<Gicv3Redistributor *> redistributors;
51    std::vector<Gicv3CPUInterface *> cpuInterfaces;
52    Gicv3Its * its;
53    AddrRange distRange;
54    AddrRange redistRange;
55    AddrRangeList addrRanges;
56    uint64_t redistSize;
57
58  public:
59
60    // Special interrupt IDs, as per SPEC 2.2.1 section
61    static const int INTID_SECURE = 1020;
62    static const int INTID_NONSECURE = 1021;
63    static const int INTID_SPURIOUS = 1023;
64
65    // Number of Software Generated Interrupts
66    static const int SGI_MAX = 16;
67    // Number of Private Peripheral Interrupts
68    static const int PPI_MAX = 16;
69
70    // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
71    typedef enum {
72        INT_INACTIVE,
73        INT_PENDING,
74        INT_ACTIVE,
75        INT_ACTIVE_PENDING,
76    } IntStatus;
77
78    // Interrupt groups, as per SPEC section 4.6
79    typedef enum {
80        G0S,
81        G1S,
82        G1NS,
83    } GroupId;
84
85    typedef enum {
86        INT_LEVEL_SENSITIVE,
87        INT_EDGE_TRIGGERED,
88    } IntTriggerType;
89
90  protected:
91
92    void clearInt(uint32_t int_id) override;
93    void clearPPInt(uint32_t int_id, uint32_t cpu) override;
94
95    inline AddrRangeList
96    getAddrRanges() const override
97    {
98        return addrRanges;
99    }
100
101    void init() override;
102    void initState() override;
103
104    const Params *
105    params() const
106    {
107        return dynamic_cast<const Params *>(_params);
108    }
109
110    Tick read(PacketPtr pkt) override;
111    void reset();
112    void sendInt(uint32_t int_id) override;
113    void sendPPInt(uint32_t int_id, uint32_t cpu) override;
114    void serialize(CheckpointOut & cp) const override;
115    void unserialize(CheckpointIn & cp) override;
116    Tick write(PacketPtr pkt) override;
117
118  public:
119
120    Gicv3(const Params * p);
121    void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
122
123    inline Gicv3CPUInterface *
124    getCPUInterface(int cpu_id) const
125    {
126        assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
127        return cpuInterfaces[cpu_id];
128    }
129
130    inline Gicv3Distributor *
131    getDistributor() const
132    {
133        return distributor;
134    }
135
136    inline Gicv3Redistributor *
137    getRedistributor(ContextID context_id) const
138    {
139        assert(context_id < redistributors.size() and
140               redistributors[context_id]);
141        return redistributors[context_id];
142    }
143
144    Gicv3Redistributor *
145    getRedistributorByAffinity(uint32_t affinity) const;
146
147    Gicv3Redistributor *
148    getRedistributorByAddr(Addr address) const;
149
150    void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
151};
152
153#endif //__DEV_ARM_GICV3_H__
154