gic_v3.hh revision 13826:34a9929c35eb 
1/*
2 * Copyright (c) 2018 Metempsy Technology Consulting
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Jairo Balart
29 */
30
31#ifndef __DEV_ARM_GICV3_H__
32#define __DEV_ARM_GICV3_H__
33
34#include "dev/arm/base_gic.hh"
35#include "params/Gicv3.hh"
36
37class Gicv3CPUInterface;
38class Gicv3Distributor;
39class Gicv3Redistributor;
40
41class Gicv3 : public BaseGic
42{
43  protected:
44    friend class Gicv3CPUInterface;
45
46    typedef Gicv3Params Params;
47    Gicv3Distributor * distributor;
48    std::vector<Gicv3Redistributor *> redistributors;
49    std::vector<Gicv3CPUInterface *> cpuInterfaces;
50    AddrRange distRange;
51    AddrRange redistRange;
52    AddrRangeList addrRanges;
53
54  public:
55
56    // Special interrupt IDs, as per SPEC 2.2.1 section
57    static const int INTID_SECURE = 1020;
58    static const int INTID_NONSECURE = 1021;
59    static const int INTID_SPURIOUS = 1023;
60
61    // Number of Software Generated Interrupts
62    static const int SGI_MAX = 16;
63    // Number of Private Peripheral Interrupts
64    static const int PPI_MAX = 16;
65
66    // Interrupt states for PPIs, SGIs and SPIs, as per SPEC 4.1.2 section
67    typedef enum {
68        INT_INACTIVE,
69        INT_PENDING,
70        INT_ACTIVE,
71        INT_ACTIVE_PENDING,
72    } IntStatus;
73
74    // Interrupt groups, as per SPEC section 4.6
75    typedef enum {
76        G0S,
77        G1S,
78        G1NS,
79    } GroupId;
80
81    typedef enum {
82        INT_LEVEL_SENSITIVE,
83        INT_EDGE_TRIGGERED,
84    } IntTriggerType;
85
86  protected:
87
88    void clearInt(uint32_t int_id) override;
89    void clearPPInt(uint32_t int_id, uint32_t cpu) override;
90
91    inline AddrRangeList
92    getAddrRanges() const override
93    {
94        return addrRanges;
95    }
96
97    void init() override;
98    void initState() override;
99
100    const Params *
101    params() const
102    {
103        return dynamic_cast<const Params *>(_params);
104    }
105
106    Tick read(PacketPtr pkt) override;
107    void reset();
108    void sendInt(uint32_t int_id) override;
109    void sendPPInt(uint32_t int_id, uint32_t cpu) override;
110    void serialize(CheckpointOut & cp) const override;
111    void unserialize(CheckpointIn & cp) override;
112    Tick write(PacketPtr pkt) override;
113
114  public:
115
116    Gicv3(const Params * p);
117    void deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
118
119    inline Gicv3CPUInterface *
120    getCPUInterface(int cpu_id) const
121    {
122        assert(cpu_id < cpuInterfaces.size() and cpuInterfaces[cpu_id]);
123        return cpuInterfaces[cpu_id];
124    }
125
126    inline Gicv3Distributor *
127    getDistributor() const
128    {
129        return distributor;
130    }
131
132    inline Gicv3Redistributor *
133    getRedistributor(ContextID context_id) const
134    {
135        assert(context_id < redistributors.size() and
136               redistributors[context_id]);
137        return redistributors[context_id];
138    }
139
140    Gicv3Redistributor *
141    getRedistributorByAffinity(uint32_t affinity) const;
142    void postInt(uint32_t cpu, ArmISA::InterruptTypes int_type);
143};
144
145#endif //__DEV_ARM_GICV3_H__
146